📄 x444_to_422_to_444.mdl
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Position [150, 193, 180, 207]
Port "3"
}
Line {
SrcBlock "Y_4i"
SrcPort 1
DstBlock "Delay"
DstPort 1
}
Line {
SrcBlock "Cb_4i"
SrcPort 1
DstBlock "Down Sample1"
DstPort 1
}
Line {
SrcBlock "Down Sample1"
SrcPort 1
DstBlock "Cb_2o"
DstPort 1
}
Line {
SrcBlock "Cr_4i"
SrcPort 1
DstBlock "Down Sample2"
DstPort 1
}
Line {
SrcBlock "Down Sample2"
SrcPort 1
DstBlock "Cr_2o"
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
DstBlock "Y_4o"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "YCrCb_to_RGB"
Ports [3, 3]
Position [1015, 166, 1085, 364]
TreatAsAtomicUnit off
System {
Name "YCrCb_to_RGB"
Location [5, 275, 459, 580]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 282
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "81"
Block {
BlockType Inport
Name "Y"
Position [45, 43, 75, 57]
}
Block {
BlockType Inport
Name "Cb"
Position [50, 318, 80, 332]
Port "2"
}
Block {
BlockType Inport
Name "Cr"
Position [50, 113, 80, 127]
Port "3"
}
Block {
BlockType Reference
Name "AddSub"
Ports [2, 1]
Position [185, 37, 235, 88]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Subtraction"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "1"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "AddSub1"
Ports [2, 1]
Position [185, 107, 235, 158]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Subtraction"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "1"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "AddSub2"
Ports [2, 1]
Position [185, 312, 235, 363]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Subtraction"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "1"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "AddSub3"
Ports [2, 1]
Position [655, 112, 705, 163]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Addition"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "2"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "AddSub4"
Ports [2, 1]
Position [655, 247, 705, 298]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Subtraction"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "1"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "AddSub5"
Ports [2, 1]
Position [660, 317, 710, 368]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Addition"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "2"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "AddSub6"
Ports [2, 1]
Position [555, 182, 605, 233]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Subtraction"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "1"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Constant"
Ports [0, 1]
Position [100, 60, 145, 90]
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "2^Image_bits/16"
arith_type "Unsigned"
n_bits "Image_bits"
bin_pt "0"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Constant1"
Ports [0, 1]
Position [250, 74, 355, 106]
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "1.164"
arith_type "Signed (2's comp)"
n_bits "c_resol+2"
bin_pt "c_resol"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Constant2"
Ports [0, 1]
Position [100, 130, 145, 160]
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "2^Image_bits/2"
arith_type "Unsigned"
n_bits "Image_bits"
bin_pt "0"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Constant3"
Ports [0, 1]
Position [250, 144, 355, 176]
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "1.596"
arith_type "Signed (2's comp)"
n_bits "c_resol+2"
bin_pt "c_resol"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Constant4"
Ports [0, 1]
Position [100, 335, 145, 365]
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "2^Image_bits/2"
arith_type "Unsigned"
n_bits "Image_bits"
bin_pt "0"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Constant5"
Ports [0, 1]
Position [250, 349, 355, 381]
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "2.017"
arith_type "Signed (2's comp)"
n_bits "c_resol+3"
bin_pt "c_resol"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Constant6"
Ports [0, 1]
Position [250, 214, 355, 246]
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "0.813"
arith_type "Signed (2's comp)"
n_bits "c_resol+2"
bin_pt "c_resol"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Constant7"
Ports [0, 1]
Position [250, 279, 355, 311]
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "0.392"
arith_type "Signed (2's comp)"
n_bits "c_resol+2"
bin_pt "c_resol"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "P1"
Ports [2, 1]
Position [400, 52, 450, 103]
SourceBlock "xbsIndex_r3/Mult"
SourceType "Xilinx Multiplier"
precision "Full"
arith_type "Signed (2's comp)"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "3"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
mult_type "Parallel"
oversample "2"
use_embedded on
pipeline on
use_rpm on
placement_style "Rectangular Shape"
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "P2"
Ports [2, 1]
Position [400, 122, 450, 173]
SourceBlock "xbsIndex_r3/Mult"
SourceType "Xilinx Multiplier"
precision "Full"
arith_type "Signed (2's comp)"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "3"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
mult_type "Parallel"
oversample "2"
use_embedded on
pipeline on
use_rpm on
placement_style "Rectangular Shape"
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "P3"
Ports [2, 1]
Position [400, 192, 450, 243]
SourceBlock "xbsIndex_r3/Mult"
SourceType "Xilinx Multiplier"
precision "Full"
arith_type "Signed (2's comp)"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "3"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
mult_type "Parallel"
oversample "2"
use_embedded on
pipeline on
use_rpm on
placement_style "Rectangular Shape"
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "P4"
Ports [2, 1]
Position [400, 257, 450, 308]
SourceBlock "xbsIndex_r3/Mult"
SourceType "Xilinx Multiplier"
precision "Full"
arith_type "Signed (2's comp)"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "3"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
mult_type "Parallel"
oversample "2"
use_embedded on
pipeline on
use_rpm on
placement_style "Rectangular Shape"
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
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