📄 x444_to_422_to_444.mdl
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dbl_ovrd on
}
Block {
BlockType Reference
Name "o_resol_value"
Ports [0, 1]
Position [400, 150, 445, 180]
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "o_resol"
arith_type "Unsigned"
n_bits "8"
bin_pt "1"
explicit_period off
period "1"
dbl_ovrd on
}
Block {
BlockType Outport
Name "Y"
Position [555, 248, 585, 262]
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BlockType Outport
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Port "2"
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BlockType Outport
Name "Cr"
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SrcBlock "AddSub8"
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DstBlock "Cr"
DstPort 1
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Line {
SrcBlock "AddSub5"
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DstBlock "Cb"
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Points [10, 0; 0, -55]
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DstPort 1
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Line {
SrcBlock "CMult5"
SrcPort 1
Points [15, 0; 0, -20]
DstBlock "AddSub3"
DstPort 2
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Line {
SrcBlock "CMult4"
SrcPort 1
Points [15, 0; 0, 30]
DstBlock "AddSub3"
DstPort 1
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Line {
SrcBlock "CMult3"
SrcPort 1
DstBlock "AddSub4"
DstPort 2
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Line {
SrcBlock "Constant1"
SrcPort 1
Points [20, 0; 0, 55]
DstBlock "AddSub4"
DstPort 1
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Line {
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SrcPort 1
DstBlock "Y"
DstPort 1
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DstPort 2
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SrcBlock "AddSub1"
SrcPort 1
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DstBlock "AddSub2"
DstPort 1
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SrcBlock "CMult2"
SrcPort 1
Points [15, 0; 0, -20]
DstBlock "AddSub"
DstPort 2
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Line {
SrcBlock "CMult1"
SrcPort 1
Points [15, 0; 0, 30]
DstBlock "AddSub"
DstPort 1
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Line {
SrcBlock "CMult"
SrcPort 1
DstBlock "AddSub1"
DstPort 2
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Line {
SrcBlock "Constant"
SrcPort 1
Points [20, 0; 0, 55]
DstBlock "AddSub1"
DstPort 1
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Line {
SrcBlock "B"
SrcPort 1
Points [55, 0]
Branch {
Points [0, 150]
Branch {
Points [0, 460]
DstBlock "CMult8"
DstPort 1
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Branch {
DstBlock "CMult3"
DstPort 1
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Branch {
DstBlock "CMult2"
DstPort 1
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Line {
SrcBlock "G"
SrcPort 1
Points [10, 0]
Branch {
Points [0, 380]
Branch {
Points [0, 230]
DstBlock "CMult7"
DstPort 1
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Branch {
DstBlock "CMult5"
DstPort 1
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Branch {
DstBlock "CMult1"
DstPort 1
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Line {
SrcBlock "R"
SrcPort 1
Points [35, 0]
Branch {
Points [0, 385]
Branch {
DstBlock "CMult4"
DstPort 1
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Branch {
Points [0, 225]
DstBlock "CMult6"
DstPort 1
}
}
Branch {
DstBlock "CMult"
DstPort 1
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}
Block {
BlockType Reference
Name "Signal From\nWorkspace"
Ports [0, 1]
Position [15, 182, 140, 218]
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
X "double(fpga_input_red)"
Ts "System_Period"
nsamps "1"
OutputAfterFinalValue "Setting to zero"
}
Block {
BlockType Reference
Name "Signal From\nWorkspace1"
Ports [0, 1]
Position [15, 247, 140, 283]
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
X "double(fpga_input_grn)"
Ts "System_Period"
nsamps "1"
OutputAfterFinalValue "Setting to zero"
}
Block {
BlockType Reference
Name "Signal From\nWorkspace2"
Ports [0, 1]
Position [15, 312, 140, 348]
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
X "double(fpga_input_blu)"
Ts "System_Period"
nsamps "1"
OutputAfterFinalValue "Setting to zero"
}
Block {
BlockType SubSystem
Name "YCbCr\n422_to_444\nSimple Replication"
Ports [3, 3]
Position [780, 167, 850, 363]
BackgroundColor "red"
TreatAsAtomicUnit off
System {
Name "YCbCr\n422_to_444\nSimple Replication"
Location [230, 99, 928, 766]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
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BlockType Inport
Name "Y_4i"
Position [25, 43, 55, 57]
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Block {
BlockType Inport
Name "Cb_2i"
Position [25, 108, 55, 122]
Port "2"
}
Block {
BlockType Inport
Name "Cr_2i"
Position [25, 173, 55, 187]
Port "3"
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [80, 27, 125, 73]
SourceBlock "xbsIndex_r3/Delay"
SourceType "Xilinx Delay Block"
latency "1"
reg_retiming off
explicit_period off
period "1"
en off
accept_only_valid off
init_zero on
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Up Sample1"
Ports [1, 1]
Position [80, 92, 125, 138]
SourceBlock "xbsIndex_r3/Up Sample"
SourceType "Xilinx Up Sampling Block"
sample_ratio "2"
copy_samples on
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Up Sample2"
Ports [1, 1]
Position [80, 157, 125, 203]
SourceBlock "xbsIndex_r3/Up Sample"
SourceType "Xilinx Up Sampling Block"
sample_ratio "2"
copy_samples on
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Outport
Name "Y_4o"
Position [150, 43, 180, 57]
}
Block {
BlockType Outport
Name "Cb_4o"
Position [150, 108, 180, 122]
Port "2"
}
Block {
BlockType Outport
Name "Cr_4o"
Position [150, 173, 180, 187]
Port "3"
}
Line {
SrcBlock "Y_4i"
SrcPort 1
DstBlock "Delay"
DstPort 1
}
Line {
SrcBlock "Cb_2i"
SrcPort 1
DstBlock "Up Sample1"
DstPort 1
}
Line {
SrcBlock "Up Sample1"
SrcPort 1
DstBlock "Cb_4o"
DstPort 1
}
Line {
SrcBlock "Cr_2i"
SrcPort 1
DstBlock "Up Sample2"
DstPort 1
}
Line {
SrcBlock "Up Sample2"
SrcPort 1
DstBlock "Cr_4o"
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
DstBlock "Y_4o"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "YCbCr\n444_to_422"
Ports [3, 3]
Position [545, 165, 605, 365]
BackgroundColor "red"
TreatAsAtomicUnit off
System {
Name "YCbCr\n444_to_422"
Location [202, 82, 1014, 744]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "Y_4i"
Position [25, 43, 55, 57]
}
Block {
BlockType Inport
Name "Cb_4i"
Position [25, 118, 55, 132]
Port "2"
}
Block {
BlockType Inport
Name "Cr_4i"
Position [25, 193, 55, 207]
Port "3"
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [80, 27, 125, 73]
SourceBlock "xbsIndex_r3/Delay"
SourceType "Xilinx Delay Block"
latency "1"
reg_retiming off
explicit_period off
period "1"
en off
accept_only_valid off
init_zero on
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Down Sample1"
Ports [1, 1]
Position [80, 101, 125, 149]
SourceBlock "xbsIndex_r3/Down Sample"
SourceType "Xilinx Down Sampling Block"
sample_ratio "2"
sample_phase "First Value of Frame"
latency "1"
en off
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Down Sample2"
Ports [1, 1]
Position [80, 176, 125, 224]
SourceBlock "xbsIndex_r3/Down Sample"
SourceType "Xilinx Down Sampling Block"
sample_ratio "2"
sample_phase "First Value of Frame"
latency "1"
en off
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Outport
Name "Y_4o"
Position [150, 43, 180, 57]
}
Block {
BlockType Outport
Name "Cb_2o"
Position [150, 118, 180, 132]
Port "2"
}
Block {
BlockType Outport
Name "Cr_2o"
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