📄 x444_to_422_to_444.mdl
字号:
Model {
Name "x444_to_422_to_444"
Version 5.1
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes on
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
SortedOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks on
PreLoadFcn "xlrequire('PreLoadFcn')"
StartFcn "xlrequire('PreLoadFcn'),tic"
StopFcn "toc,xlrequire('StopFcn')"
Created "Thu Apr 15 11:50:58 2004"
Creator "Daniel Michek"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "danielm"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Thu Aug 19 10:07:51 2004"
ModelVersionFormat "1.%<AutoIncrement:69>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "32868"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
VectorParams1D on
}
Block {
BlockType EnablePort
StatesWhenEnabling "held"
ShowOutputPort off
ZeroCross on
}
Block {
BlockType FrameConversion
OutFrame "Frame-based"
}
Block {
BlockType FromWorkspace
VariableName "simulink_input"
Interpolate on
OutputAfterFinalValue "Extrapolation"
}
Block {
BlockType Inport
Port "1"
PortDimensions "-1"
ShowAdditionalParam off
LatchInput off
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
VectorParams1D on
ZeroCross on
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Terminator
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "x444_to_422_to_444"
Location [202, 78, 1014, 740]
Open on
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "67"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name " System Generator"
Tag "genX"
Ports []
Position [282, 28, 333, 78]
ShowName off
AttributesFormatString "System\\nGenerator"
UserDataPersistent on
UserData "DataTag0"
SourceBlock "xbsIndex_r3/ System Generator"
SourceType "Xilinx System Generator"
xilinxfamily "Virtex2"
part "xc2v1000"
speed "-4"
package "bg575"
synthesis_tool "XST"
directory "./netlist"
testbench off
simulink_period "1/9"
sysclk_period "100"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
}
Block {
BlockType SubSystem
Name "RGBga to YCbCr\n444_to_444"
Ports [3, 3]
Position [305, 170, 360, 360]
BackgroundColor "red"
TreatAsAtomicUnit off
MaskType "Xilinx Video Applications Block: XAPP637"
MaskDescription "XAPP637 Color Space Converter: R'G'B' to Y'CbCr"
"\n\nThis application note describes the implementation of R'G'B' Color Space "
"to Y'CbCr Color Space conversion necessary in many video designs. The tick ma"
"rks on red, green, blue, and Luma, assume the components are in the gamma cor"
"rected space. No gamma correction is applied to color difference signals Cr "
"and Cb. \n\nThe reference design files show RTL (VHDL and Verilog) code to d"
"escribe the conversion equations and synthesize to a target FPGA. The code is"
" parameterizable for the input/output precision (8 bit or 10 bit) and the int"
"ernal coefficient precision (8 to 13 bits have been defined). Simulation tes"
"t vectors (25%, 50%, 75%, and 100% RGB Color Bars) are also provided in the r"
"eference design file to confirm compliance to ITU-R BT.601-2 component video "
"standards (SDTV)[3].\n\nAs an implementation example, placed and routed desig"
"n in a Spartan-IIE device (2S50E-6TQ144) takes about 20% of that device (150 "
"slices) and clock performance of 99 MHz using simple constraints (8-bit input"
"/output and 8-bit internal coefficients).\n\nHDTV color space coefficients ar"
"e different (covered in BT.709-3, June 1990). This application note does not "
"cover this area."
MaskHelp "http://www.xilinx.com/xapp/xapp637.pdf"
MaskPromptString "Input/Output Resolution (8 or 10)|Coefficient R"
"esolution (8-13)"
MaskStyleString "edit,edit"
MaskTunableValueString "on,on"
MaskCallbackString "|"
MaskEnableString "on,on"
MaskVisibilityString "on,on"
MaskToolTipString "on,on"
MaskVarAliasString ","
MaskVariables "o_resol=@1;c_resol=@2;"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
MaskValueString "Image_bits|c_resol"
System {
Name "RGBga to YCbCr\n444_to_444"
Location [202, 84, 889, 546]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "76"
Block {
BlockType Inport
Name "R"
Position [25, 188, 55, 202]
}
Block {
BlockType Inport
Name "G"
Position [25, 268, 55, 282]
Port "2"
}
Block {
BlockType Inport
Name "B"
Position [25, 343, 55, 357]
Port "3"
}
Block {
BlockType Reference
Name "AddSub"
Ports [2, 1]
Position [255, 292, 305, 343]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Addition"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "1"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core on
xl_area "[11 21 0 20 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "AddSub1"
Ports [2, 1]
Position [260, 157, 310, 208]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Addition"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "1"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core on
xl_area "[11 21 0 20 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "AddSub2"
Ports [2, 1]
Position [345, 227, 395, 278]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Addition"
precision "User Defined"
arith_type "Unsigned"
n_bits "o_resol"
bin_pt "0"
quantization "Truncate"
overflow "Wrap"
latency "1"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core on
xl_area "[10 8 0 20 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "AddSub3"
Ports [2, 1]
Position [255, 597, 305, 648]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Addition"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "1"
explicit_period off
period "1"
use_carryin off
use_carryout off
en off
dbl_ovrd off
show_param off
use_core on
pipeline off
use_rpm off
gen_core on
xl_area "[11 21 0 20 0 0 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "AddSub4"
Ports [2, 1]
Position [260, 462, 310, 513]
SourceBlock "xbsIndex_r3/AddSub"
SourceType "Xilinx Adder/Subtractor"
mode "Addition"
precision "Full"
arith_type "Unsigned"
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -