📄 freq.rpt
字号:
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\freq\freq.rpt
freq
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A23 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 2/2 1/2 2/22( 9%)
B1 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 12/22( 54%)
B2 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 11/22( 50%)
B3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
B4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
B6 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 15/22( 68%)
B7 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 14/22( 63%)
B8 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
B10 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 1/2 16/22( 72%)
B11 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
B12 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 7/22( 31%)
B13 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
B14 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 6/22( 27%)
B15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
B16 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 0/2 0/2 5/22( 22%)
B17 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 13/22( 59%)
B18 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 1/2 3/22( 13%)
B19 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 12/22( 54%)
B20 7/ 8( 87%) 3/ 8( 37%) 5/ 8( 62%) 1/2 1/2 5/22( 22%)
B21 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 12/22( 54%)
B22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
B23 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 17/22( 77%)
B24 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
C13 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
C14 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 13/22( 59%)
C16 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
C17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C19 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
C21 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 15/22( 68%)
C22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
C23 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 12/22( 54%)
C24 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 14/22( 63%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 14/128 ( 10%)
Total logic cells used: 233/576 ( 40%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 786/2304 ( 34%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 11
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 233
Total flipflops required: 32
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 36/ 576 ( 6%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8/0
B: 8 8 8 1 8 8 8 7 0 8 8 2 0 8 8 8 8 8 8 8 7 8 8 8 6 167/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 0 8 1 0 7 0 8 8 8 8 58/0
Total: 8 8 8 1 8 8 8 7 0 8 8 2 0 10 16 8 16 9 8 15 7 16 16 24 14 233/0
Device-Specific Information: e:\freq\freq.rpt
freq
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
10 - - A -- INPUT 0 0 0 1 clk
11 - - A -- INPUT 0 0 0 27 fsin
12 - - A -- INPUT 0 0 0 7 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\freq\freq.rpt
freq
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
13 - - A -- OUTPUT 0 1 0 0 row0
16 - - A -- OUTPUT 0 1 0 0 row1
17 - - A -- OUTPUT 0 1 0 0 row2
25 - - B -- OUTPUT 0 1 0 0 show0
26 - - B -- OUTPUT 0 1 0 0 show1
27 - - B -- OUTPUT 0 1 0 0 show2
28 - - B -- OUTPUT 0 1 0 0 show3
29 - - B -- OUTPUT 0 1 0 0 show4
30 - - B -- OUTPUT 0 1 0 0 show5
31 - - B -- OUTPUT 0 1 0 0 show6
38 - - C -- OUTPUT 0 1 0 0 show7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\freq\freq.rpt
freq
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 19 OR2 0 4 0 4 |LPM_ADD_SUB:1743|addcore:adder|:163
- 4 - B 11 OR2 0 4 0 2 |LPM_ADD_SUB:1743|addcore:adder|:179
- 3 - B 17 OR2 0 4 0 2 |LPM_ADD_SUB:1743|addcore:adder|:195
- 8 - B 17 OR2 0 4 0 2 |LPM_ADD_SUB:1743|addcore:adder|:211
- 1 - C 17 AND2 0 2 0 2 |LPM_ADD_SUB:1743|addcore:adder|:215
- 3 - C 23 OR2 0 3 0 1 |LPM_ADD_SUB:1743|addcore:adder|:249
- 5 - B 21 AND2 0 2 0 2 |LPM_ADD_SUB:1864|addcore:adder|:199
- 1 - B 21 AND2 0 2 0 2 |LPM_ADD_SUB:1864|addcore:adder|:203
- 2 - C 14 AND2 0 2 0 2 |LPM_ADD_SUB:1864|addcore:adder|:207
- 2 - C 19 AND2 0 2 0 2 |LPM_ADD_SUB:1864|addcore:adder|:211
- 1 - C 19 AND2 0 2 0 2 |LPM_ADD_SUB:1864|addcore:adder|:215
- 6 - B 01 AND2 0 2 0 2 |LPM_ADD_SUB:1985|addcore:adder|:183
- 4 - B 01 AND2 0 2 0 4 |LPM_ADD_SUB:1985|addcore:adder|:187
- 5 - B 07 AND2 0 3 0 1 |LPM_ADD_SUB:1985|addcore:adder|:195
- 4 - B 21 AND2 0 4 0 2 |LPM_ADD_SUB:1985|addcore:adder|:199
- 6 - B 21 AND2 0 2 0 2 |LPM_ADD_SUB:1985|addcore:adder|:203
- 6 - C 19 AND2 0 2 0 2 |LPM_ADD_SUB:1985|addcore:adder|:207
- 8 - C 19 AND2 0 2 0 2 |LPM_ADD_SUB:1985|addcore:adder|:211
- 4 - C 19 AND2 0 2 0 2 |LPM_ADD_SUB:1985|addcore:adder|:215
- 7 - C 22 OR2 0 3 0 1 |LPM_ADD_SUB:1985|addcore:adder|:249
- 3 - B 19 OR2 0 4 0 2 |LPM_ADD_SUB:2106|addcore:adder|:147
- 8 - B 11 AND2 0 2 0 1 |LPM_ADD_SUB:2106|addcore:adder|:167
- 3 - B 11 AND2 0 4 0 2 |LPM_ADD_SUB:2106|addcore:adder|:175
- 2 - B 05 AND2 0 2 0 3 |LPM_ADD_SUB:2106|addcore:adder|:179
- 8 - B 08 AND2 0 3 0 4 |LPM_ADD_SUB:2106|addcore:adder|:187
- 2 - B 07 AND2 0 3 0 1 |LPM_ADD_SUB:2106|addcore:adder|:195
- 7 - B 07 AND2 0 4 0 2 |LPM_ADD_SUB:2106|addcore:adder|:199
- 5 - C 14 AND2 0 2 0 2 |LPM_ADD_SUB:2106|addcore:adder|:203
- 4 - C 14 AND2 0 2 0 2 |LPM_ADD_SUB:2106|addcore:adder|:207
- 1 - C 24 AND2 0 2 0 2 |LPM_ADD_SUB:2106|addcore:adder|:211
- 5 - C 21 AND2 0 2 0 2 |LPM_ADD_SUB:2106|addcore:adder|:215
- 6 - B 11 OR2 0 4 0 1 |LPM_ADD_SUB:2106|addcore:adder|:237
- 3 - B 01 OR2 0 3 0 1 |LPM_ADD_SUB:2106|addcore:adder|:240
- 2 - B 06 OR2 0 3 0 1 |LPM_ADD_SUB:2106|addcore:adder|:242
- 5 - C 22 OR2 0 3 0 1 |LPM_ADD_SUB:2106|addcore:adder|:249
- 5 - B 19 AND2 0 2 0 2 |LPM_ADD_SUB:2227|addcore:adder|:151
- 4 - B 19 AND2 0 2 0 2 |LPM_ADD_SUB:2227|addcore:adder|:155
- 3 - B 03 AND2 0 2 0 2 |LPM_ADD_SUB:2227|addcore:adder|:159
- 2 - B 03 AND2 0 2 0 3 |LPM_ADD_SUB:2227|addcore:adder|:163
- 6 - B 10 AND2 0 2 0 2 |LPM_ADD_SUB:2227|addcore:adder|:167
- 5 - B 10 AND2 0 4 0 2 |LPM_ADD_SUB:2227|addcore:adder|:175
- 3 - B 10 AND2 0 2 0 4 |LPM_ADD_SUB:2227|addcore:adder|:179
- 2 - B 08 AND2 0 3 0 1 |LPM_ADD_SUB:2227|addcore:adder|:187
- 8 - B 10 AND2 0 4 0 2 |LPM_ADD_SUB:2227|addcore:adder|:191
- 4 - B 10 AND2 0 2 0 2 |LPM_ADD_SUB:2227|addcore:adder|:195
- 4 - C 16 AND2 0 2 0 2 |LPM_ADD_SUB:2227|addcore:adder|:199
- 6 - C 16 AND2 0 2 0 2 |LPM_ADD_SUB:2227|addcore:adder|:203
- 8 - C 16 AND2 0 2 0 2 |LPM_ADD_SUB:2227|addcore:adder|:207
- 2 - C 24 AND2 0 2 0 2 |LPM_ADD_SUB:2227|addcore:adder|:211
- 2 - C 21 AND2 0 2 0 2 |LPM_ADD_SUB:2227|addcore:adder|:215
- 5 - B 18 AND2 0 2 0 1 |LPM_ADD_SUB:2348|addcore:adder|:135
- 4 - B 18 AND2 0 3 0 1 |LPM_ADD_SUB:2348|addcore:adder|:139
- 7 - B 18 AND2 0 4 0 4 |LPM_ADD_SUB:2348|addcore:adder|:143
- 6 - B 24 AND2 0 3 0 1 |LPM_ADD_SUB:2348|addcore:adder|:151
- 1 - B 24 AND2 0 4 0 2 |LPM_ADD_SUB:2348|addcore:adder|:155
- 8 - B 03 AND2 0 2 0 2 |LPM_ADD_SUB:2348|addcore:adder|:159
- 5 - B 11 AND2 0 2 0 3 |LPM_ADD_SUB:2348|addcore:adder|:163
- 3 - B 02 AND2 0 2 0 2 |LPM_ADD_SUB:2348|addcore:adder|:167
- 2 - B 11 AND2 0 4 0 2 |LPM_ADD_SUB:2348|addcore:adder|:175
- 7 - B 05 AND2 0 2 0 4 |LPM_ADD_SUB:2348|addcore:adder|:179
- 3 - B 08 AND2 0 3 0 1 |LPM_ADD_SUB:2348|addcore:adder|:187
- 1 - B 06 AND2 0 4 0 2 |LPM_ADD_SUB:2348|addcore:adder|:191
- 4 - B 06 AND2 0 2 0 2 |LPM_ADD_SUB:2348|addcore:adder|:195
- 2 - C 16 AND2 0 2 0 2 |LPM_ADD_SUB:2348|addcore:adder|:199
- 3 - C 16 AND2 0 2 0 2 |LPM_ADD_SUB:2348|addcore:adder|:203
- 5 - C 16 AND2 0 2 0 2 |LPM_ADD_SUB:2348|addcore:adder|:207
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