count49.vhd

来自「近百个vhdl的器件编程,虽然个别较为简单,但都很实用,对于初学者会有很大帮助」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count49 is
port(clock, clear : in std_logic;
cnt1to49 : buffer std_logic_vector(7 downto 0));
end entity count49;
architecture v1 of count49 is
begin
count_proc : process
begin
             wait until rising_edge(clock);
               if (clear = '1') or (cnt1to49 = X"49") then
                  cnt1to49 <= (0 => '1', others => '0');
                 elsif cnt1to49(3 downto 0) = 9 then
               cnt1to49(3 downto 0) <= (0 => '1', others => '0');
             cnt1to49(7 downto 4) <= cnt1to49(7 downto 4) + 1;
            else
            cnt1to49(3 downto 0) <= cnt1to49(3 downto 0) + 1;
end if;
end process;
end architecture v1;