📄 mb.rpt
字号:
4 16 A FF t 0 0 0 1 6 6 0 Q10
41 64 D FF t 0 0 0 1 8 6 0 Q11
33 49 D FF t 0 0 0 1 4 7 1 Q12
39 57 D FF t 0 0 0 1 8 7 1 Q13
36 52 D FF t 0 0 0 1 8 7 1 Q14
34 51 D FF t 1 0 1 1 9 7 1 Q15
37 53 D FF t 0 0 0 1 4 7 0 Q16
25 35 C FF t 0 0 0 1 8 7 0 Q17
27 37 C FF t 0 0 0 1 6 6 0 Q18
31 46 C FF t 0 0 0 1 8 6 0 Q19
29 41 C FF t 0 0 0 1 4 3 1 Q20
26 36 C FF t 0 0 0 1 8 3 1 Q21
24 33 C FF t 0 0 0 1 8 3 1 Q22
28 40 C FF t 1 0 1 1 9 3 1 Q23
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\mb\mb.rpt
mb
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 60 D SOFT t 0 0 0 0 4 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3
- 55 D SOFT t 0 0 0 0 5 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node4
- 50 D SOFT t 0 0 0 0 6 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node5
(11) 3 A SOFT t 0 0 0 0 7 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node6
- 2 A SOFT t 0 0 0 0 8 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node7
- 45 C SOFT t 0 0 0 0 9 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node0
- 39 C SOFT t 0 0 0 0 10 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node1
- 42 C SOFT t 0 0 0 0 11 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node2
- 44 C SOFT t 0 0 0 0 12 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node3
- 47 C SOFT t 0 0 0 0 13 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node4
(32) 48 C SOFT t 0 0 0 0 14 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node5
- 43 C SOFT t 0 0 0 0 15 0 1 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node6
- 34 C DFFE + t 0 0 0 0 16 4 13 |CLKGEN:4|TEMP14 (|CLKGEN:4|:3)
(13) 32 B DFFE + t 0 0 0 0 16 4 14 |CLKGEN:4|TEMP13 (|CLKGEN:4|:4)
- 22 B DFFE + t 0 0 0 0 16 4 15 |CLKGEN:4|TEMP12 (|CLKGEN:4|:5)
- 23 B DFFE + t 0 0 0 0 16 4 16 |CLKGEN:4|TEMP11 (|CLKGEN:4|:6)
- 26 B DFFE + t 0 0 0 0 16 4 17 |CLKGEN:4|TEMP10 (|CLKGEN:4|:7)
- 18 B DFFE + t 0 0 0 0 16 4 18 |CLKGEN:4|TEMP9 (|CLKGEN:4|:8)
- 29 B DFFE + t 0 0 0 0 16 4 19 |CLKGEN:4|TEMP8 (|CLKGEN:4|:9)
- 28 B DFFE + t 0 0 0 0 16 4 20 |CLKGEN:4|TEMP7 (|CLKGEN:4|:10)
- 6 A DFFE + t 0 0 0 0 16 4 21 |CLKGEN:4|TEMP6 (|CLKGEN:4|:11)
- 27 B DFFE + t 0 0 0 0 16 4 22 |CLKGEN:4|TEMP5 (|CLKGEN:4|:12)
(7) 8 A DFFE + t 0 0 0 0 16 4 23 |CLKGEN:4|TEMP4 (|CLKGEN:4|:13)
- 13 A DFFE + t 0 0 0 0 16 4 24 |CLKGEN:4|TEMP3 (|CLKGEN:4|:14)
(38) 56 D TFFE + t 0 0 0 0 2 4 24 |CLKGEN:4|TEMP2 (|CLKGEN:4|:15)
- 58 D TFFE + t 0 0 0 0 1 4 25 |CLKGEN:4|TEMP1 (|CLKGEN:4|:16)
- 61 D TFFE + t 0 0 0 0 0 4 26 |CLKGEN:4|TEMP0 (|CLKGEN:4|:17)
- 38 C SOFT t 0 0 0 0 4 1 0 |CNT6:6|LPM_ADD_SUB:74|addcore:adder|addcore:adder0|result_node3
- 59 D SOFT t 0 0 0 0 4 1 0 |CNT6:8|LPM_ADD_SUB:74|addcore:adder|addcore:adder0|result_node3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\mb\mb.rpt
mb
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC3 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node6
| +------------- LC2 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node7
| | +----------- LC6 |CLKGEN:4|TEMP6
| | | +--------- LC8 |CLKGEN:4|TEMP4
| | | | +------- LC13 |CLKGEN:4|TEMP3
| | | | | +----- LC11 Q0
| | | | | | +--- LC4 Q8
| | | | | | | +- LC16 Q10
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC3 -> - - * - - - - - | * - - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node6
LC6 -> * * * * * * - - | * * * - | <-- |CLKGEN:4|TEMP6
LC8 -> * * * * * * - - | * * * * | <-- |CLKGEN:4|TEMP4
LC13 -> * * * * * * - - | * * * * | <-- |CLKGEN:4|TEMP3
LC4 -> - - - - - - * * | * - - * | <-- Q8
Pin
43 -> - - - - - - - - | - - - - | <-- CLK
1 -> - - - - - - - - | - - - - | <-- CLR
12 -> - - - - - * * * | * * * * | <-- ENA
LC60 -> - - - - * - - - | * - - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3
LC55 -> - - - * - - - - | * - - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node4
LC34 -> - - * * * * - - | * * * - | <-- |CLKGEN:4|TEMP14
LC32 -> - - * * * * - - | * * * - | <-- |CLKGEN:4|TEMP13
LC22 -> - - * * * * - - | * * * - | <-- |CLKGEN:4|TEMP12
LC23 -> - - * * * * - - | * * * - | <-- |CLKGEN:4|TEMP11
LC26 -> - - * * * * - - | * * * - | <-- |CLKGEN:4|TEMP10
LC18 -> - - * * * * - - | * * * - | <-- |CLKGEN:4|TEMP9
LC29 -> - - * * * * - - | * * * - | <-- |CLKGEN:4|TEMP8
LC28 -> - * * * * * - - | * * * - | <-- |CLKGEN:4|TEMP7
LC27 -> * * * * * * - - | * * * * | <-- |CLKGEN:4|TEMP5
LC56 -> * * * * * * - - | * * * * | <-- |CLKGEN:4|TEMP2
LC58 -> * * * * * * - - | * * * * | <-- |CLKGEN:4|TEMP1
LC61 -> * * * * * * - - | * * * * | <-- |CLKGEN:4|TEMP0
LC17 -> - - - - - - * * | * * - * | <-- Q4
LC19 -> - - - - - - * * | * * - * | <-- Q5
LC21 -> - - - - - - * * | * * - * | <-- Q6
LC20 -> - - - - - - * * | * * - * | <-- Q7
LC62 -> - - - - - - - * | * - - * | <-- Q9
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\mb\mb.rpt
mb
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC32 |CLKGEN:4|TEMP13
| +--------------------------- LC22 |CLKGEN:4|TEMP12
| | +------------------------- LC23 |CLKGEN:4|TEMP11
| | | +----------------------- LC26 |CLKGEN:4|TEMP10
| | | | +--------------------- LC18 |CLKGEN:4|TEMP9
| | | | | +------------------- LC29 |CLKGEN:4|TEMP8
| | | | | | +----------------- LC28 |CLKGEN:4|TEMP7
| | | | | | | +--------------- LC27 |CLKGEN:4|TEMP5
| | | | | | | | +------------- LC30 Q1
| | | | | | | | | +----------- LC25 Q2
| | | | | | | | | | +--------- LC24 Q3
| | | | | | | | | | | +------- LC17 Q4
| | | | | | | | | | | | +----- LC19 Q5
| | | | | | | | | | | | | +--- LC21 Q6
| | | | | | | | | | | | | | +- LC20 Q7
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC32 -> * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:4|TEMP13
LC22 -> * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:4|TEMP12
LC23 -> * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:4|TEMP11
LC26 -> * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:4|TEMP10
LC18 -> * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:4|TEMP9
LC29 -> * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:4|TEMP8
LC28 -> * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:4|TEMP7
LC27 -> * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:4|TEMP5
LC30 -> - - - - - - - - * * * * * * * | - * - - | <-- Q1
LC25 -> - - - - - - - - * * * * * * * | - * - - | <-- Q2
LC24 -> - - - - - - - - * - * * * * * | - * - - | <-- Q3
LC17 -> - - - - - - - - - - - * * * * | * * - * | <-- Q4
LC19 -> - - - - - - - - - - - - * * * | * * - * | <-- Q5
LC21 -> - - - - - - - - - - - - * * * | * * - * | <-- Q6
LC20 -> - - - - - - - - - - - - * - * | * * - * | <-- Q7
Pin
43 -> - - - - - - - - - - - - - - - | - - - - | <-- CLK
1 -> - - - - - - - - - - - - - - - | - - - - | <-- CLR
12 -> - - - - - - - - * * * * * * * | * * * * | <-- ENA
LC50 -> - - - - - - - * - - - - - - - | - * - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node5
LC2 -> - - - - - - * - - - - - - - - | - * - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node7
LC45 -> - - - - - * - - - - - - - - - | - * - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node0
LC39 -> - - - - * - - - - - - - - - - | - * - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node1
LC42 -> - - - * - - - - - - - - - - - | - * - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node2
LC44 -> - - * - - - - - - - - - - - - | - * - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node3
LC47 -> - * - - - - - - - - - - - - - | - * - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node4
LC48 -> * - - - - - - - - - - - - - - | - * - - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node5
LC34 -> * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:4|TEMP14
LC6 -> * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:4|TEMP6
LC8 -> * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:4|TEMP4
LC13 -> * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:4|TEMP3
LC56 -> * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:4|TEMP2
LC58 -> * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:4|TEMP1
LC61 -> * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:4|TEMP0
LC11 -> - - - - - - - - * * * * * * * | - * - - | <-- Q0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\mb\mb.rpt
mb
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC45 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node0
| +----------------------------- LC39 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node1
| | +--------------------------- LC42 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node2
| | | +------------------------- LC44 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node3
| | | | +----------------------- LC47 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node4
| | | | | +--------------------- LC48 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node5
| | | | | | +------------------- LC43 |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node6
| | | | | | | +----------------- LC34 |CLKGEN:4|TEMP14
| | | | | | | | +--------------- LC38 |CNT6:6|LPM_ADD_SUB:74|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | +------------- LC35 Q17
| | | | | | | | | | +----------- LC37 Q18
| | | | | | | | | | | +--------- LC46 Q19
| | | | | | | | | | | | +------- LC41 Q20
| | | | | | | | | | | | | +----- LC36 Q21
| | | | | | | | | | | | | | +--- LC33 Q22
| | | | | | | | | | | | | | | +- LC40 Q23
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC43 -> - - - - - - - * - - - - - - - - | - - * - | <-- |CLKGEN:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node6
LC34 -> - - - - - - * * - - - - - - - - | * * * - | <-- |CLKGEN:4|TEMP14
LC38 -> - - - - - - - - - - - - - - - * | - - * - | <-- |CNT6:6|LPM_ADD_SUB:74|addcore:adder|addcore:adder0|result_node3
LC35 -> - - - - - - - - - * * * * * * * | - - * - | <-- Q17
LC37 -> - - - - - - - - - * * * * * * * | - - * - | <-- Q18
LC46 -> - - - - - - - - - * - * * * * * | - - * - | <-- Q19
LC41 -> - - - - - - - - * - - - * * * * | - - * - | <-- Q20
LC36 -> - - - - - - - - * - - - - * * * | - - * - | <-- Q21
LC33 -> - - - - - - - - * - - - - * * * | - - * - | <-- Q22
LC40 -> - - - - - - - - * - - - - * * * | - - * - | <-- Q23
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLK
1 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLR
12 -> - - - - - - - - - * * * * * * * | * * * * | <-- ENA
LC32 -> - - - - - * * * - - - - - - - - | * * * - | <-- |CLKGEN:4|TEMP13
LC22 -> - - - - * * * * - - - - - - - - | * * * - | <-- |CLKGEN:4|TEMP12
LC23 -> - - - * * * * * - - - - - - - - | * * * - | <-- |CLKGEN:4|TEMP11
LC26 -> - - * * * * * * - - - - - - - - | * * * - | <-- |CLKGEN:4|TEMP10
LC18 -> - * * * * * * * - - - - - - - - | * * * - | <-- |CLKGEN:4|TEMP9
LC29 -> * * * * * * * * - - - - - - - - | * * * - | <-- |CLKGEN:4|TEMP8
LC28 -> * * * * * * * * - - - - - - - - | * * * - | <-- |CLKGEN:4|TEMP7
LC6 -> * * * * * * * * - - - - - - - - | * * * - | <-- |CLKGEN:4|TEMP6
LC27 -> * * * * * * * * - - - - - - - - | * * * * | <-- |CLKGEN:4|TEMP5
LC8 -> * * * * * * * * - - - - - - - - | * * * * | <-- |CLKGEN:4|TEMP4
LC13 -> * * * * * * * * - - - - - - - - | * * * * | <-- |CLKGEN:4|TEMP3
LC56 -> * * * * * * * * - - - - - - - - | * * * * | <-- |CLKGEN:4|TEMP2
LC58 -> * * * * * * * * - - - - - - - - | * * * * | <-- |CLKGEN:4|TEMP1
LC61 -> * * * * * * * * - - - - - - - - | * * * * | <-- |CLKGEN:4|TEMP0
LC49 -> - - - - - - - - - * * * - - - - | - - * * | <-- Q12
LC57 -> - - - - - - - - - * * * - - - - | - - * * | <-- Q13
LC52 -> - - - - - - - - - * * * - - - - | - - * * | <-- Q14
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