fifo1.vhd

para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo1 is
 port(
		clk:	in std_logic;				 				--定义控制时钟
		reset:	in std_logic;							--定义复位信号
		wr,rd:	in std_logic;							--定义读写控制信号
		din:	in std_logic_vector(7 downto 0);			--定义输入信号
		dout:	out std_logic_vector(7 downto 0);		--定义输出信号
		full:	out std_logic;							--定义FIFO满信号
		empty:	out std_logic							--定义FIFO空信号
	);
end fifo1;
architecture beh of fifo1 is
signal wp,rp:integer range 0 to 511;				--定义写指示器和读指示器
signal t:integer range 0 to 511;						--定义中间量
signal in_full,in_empty:std_logic;
signal indata:std_logic_vector(7 DOWNTO 0);
signal wrad,rdad:std_logic_vector(8 downto 0);
signal f_wr,f_rd:std_logic;
component ram_dp						--利用已生成的读写ram模块
PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
		rdaddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
		wren		: IN STD_LOGIC  ;
		rden		: IN STD_LOGIC  ;
		clock		: IN STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END component;
begin
full<=in_full;
empty<=in_empty;
u1:ram_dp 								 --对FIFO进行读写操作，上跳沿有效	
port map 
( 	data=>indata,
	wraddress=>wrad,
	rdaddress=>rdad,
	wren=>f_wr,
	rden=>f_rd,
	clock=>clk,
	q=>dout
);
process(clk)								--给ram_dp模块传送数据，下跳沿有效
begin
 if (clk'event and clk='0') then
		if (wr='1' and in_full='0') then
			indata<=din;
			f_wr<='1';
		end if;
 end if;
end process;
process(clk,reset)						   --修改wp，并传送写地址wrad，下跳沿有效
begin
 if (reset='1') then
		wp<=0;
 elsif (clk'event and clk='0' ) then
		if (wr='1' and in_full='0') then 
			wrad<=conv_std_logic_vector(wp,9);
			wp<=wp+1;
		end if;
 end if;
end process;
process(clk,reset)							--修改rp，并传送读地址rdad，下跳沿有效
begin
 if (reset='1') then
		rp<=511;
 elsif (clk'event and clk='0')	then
		if (rd='1' and in_empty='0') then
			rp<=rp+1;
			rdad<=conv_std_logic_vector(rp+1,9);
			f_rd<='1';
		end if;
 end if;
end process;
process(clk,reset) 						--产生FIFO空信号
begin
 if (reset='1') then
		in_empty<='1';
 elsif (clk'event and clk='0') then
		t<=wp-2;
		if ( rp=t and rd='1' and wr='0') then
	 		in_empty <='1';
		elsif (in_empty='1' and wr='1') then
			in_empty<='0';
 	end if;
 end if;
end process;
process(clk,reset)							--产生FIFO满信号
begin
 if (reset='1') then
		in_full<='0';
 elsif (clk'event and clk='0') then
 	if (rp=wp and wr='1' and rd='0') then
			in_full<='1';
		elsif (in_full='1' and rd='1') then
			in_full<='0';
		end if;
 end if;
end process;
end beh;