📄 shi.tan.rpt
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; N/A ; None ; -9.600 ns ; SZ[7] ; \P1:CQI[6] ; JW ;
; N/A ; None ; -9.600 ns ; SZ[7] ; \P1:CQI[7] ; JW ;
; N/A ; None ; -9.900 ns ; SZ[2] ; \P1:CQI[1] ; JW ;
; N/A ; None ; -10.100 ns ; SZ[2] ; \P1:CQI[4] ; JW ;
; N/A ; None ; -10.100 ns ; SZ[3] ; \P1:CQI[1] ; JW ;
; N/A ; None ; -10.200 ns ; SZ[2] ; \P1:CQI[5] ; JW ;
; N/A ; None ; -10.200 ns ; SZ[2] ; \P1:CQI[6] ; JW ;
; N/A ; None ; -10.200 ns ; SZ[2] ; \P1:CQI[7] ; JW ;
; N/A ; None ; -10.300 ns ; SZ[7] ; \P1:CQI[3] ; JW ;
; N/A ; None ; -10.300 ns ; SZ[7] ; \P1:CQI[2] ; JW ;
; N/A ; None ; -10.300 ns ; SZ[3] ; \P1:CQI[4] ; JW ;
; N/A ; None ; -10.400 ns ; SZ[3] ; \P1:CQI[5] ; JW ;
; N/A ; None ; -10.400 ns ; SZ[3] ; \P1:CQI[6] ; JW ;
; N/A ; None ; -10.400 ns ; SZ[3] ; \P1:CQI[7] ; JW ;
; N/A ; None ; -10.500 ns ; SZ[7] ; \P1:CQI[0] ; JW ;
; N/A ; None ; -10.900 ns ; SZ[2] ; \P1:CQI[3] ; JW ;
; N/A ; None ; -10.900 ns ; SZ[2] ; \P1:CQI[2] ; JW ;
; N/A ; None ; -11.100 ns ; SZ[2] ; \P1:CQI[0] ; JW ;
; N/A ; None ; -11.100 ns ; SZ[3] ; \P1:CQI[3] ; JW ;
; N/A ; None ; -11.100 ns ; SZ[3] ; \P1:CQI[2] ; JW ;
; N/A ; None ; -11.300 ns ; SZ[3] ; \P1:CQI[0] ; JW ;
; N/A ; None ; -11.400 ns ; SZ[6] ; \P1:CQI[1] ; JW ;
; N/A ; None ; -11.600 ns ; SZ[6] ; \P1:CQI[4] ; JW ;
; N/A ; None ; -11.700 ns ; SZ[6] ; \P1:CQI[5] ; JW ;
; N/A ; None ; -11.700 ns ; SZ[6] ; \P1:CQI[6] ; JW ;
; N/A ; None ; -11.700 ns ; SZ[6] ; \P1:CQI[7] ; JW ;
; N/A ; None ; -12.400 ns ; SZ[6] ; \P1:CQI[3] ; JW ;
; N/A ; None ; -12.400 ns ; SZ[6] ; \P1:CQI[2] ; JW ;
; N/A ; None ; -12.600 ns ; SZ[6] ; \P1:CQI[0] ; JW ;
; N/A ; None ; -12.900 ns ; SZ[1] ; \P1:CQI[1] ; JW ;
; N/A ; None ; -13.100 ns ; SZ[1] ; \P1:CQI[4] ; JW ;
; N/A ; None ; -13.200 ns ; SZ[1] ; \P1:CQI[5] ; JW ;
; N/A ; None ; -13.200 ns ; SZ[1] ; \P1:CQI[6] ; JW ;
; N/A ; None ; -13.200 ns ; SZ[1] ; \P1:CQI[7] ; JW ;
; N/A ; None ; -13.900 ns ; SZ[1] ; \P1:CQI[3] ; JW ;
; N/A ; None ; -13.900 ns ; SZ[1] ; \P1:CQI[2] ; JW ;
; N/A ; None ; -14.100 ns ; SZ[1] ; \P1:CQI[0] ; JW ;
; N/A ; None ; -14.500 ns ; SZ[0] ; \P1:CQI[1] ; JW ;
; N/A ; None ; -14.700 ns ; SZ[0] ; \P1:CQI[4] ; JW ;
; N/A ; None ; -14.800 ns ; SZ[0] ; \P1:CQI[5] ; JW ;
; N/A ; None ; -14.800 ns ; SZ[0] ; \P1:CQI[6] ; JW ;
; N/A ; None ; -14.800 ns ; SZ[0] ; \P1:CQI[7] ; JW ;
; N/A ; None ; -15.500 ns ; SZ[0] ; \P1:CQI[3] ; JW ;
; N/A ; None ; -15.500 ns ; SZ[0] ; \P1:CQI[2] ; JW ;
; N/A ; None ; -15.700 ns ; SZ[0] ; \P1:CQI[0] ; JW ;
+---------------+-------------+------------+-------+------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Sun Dec 02 20:27:44 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SHI -c SHI
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "JW" is an undefined clock
Info: Clock "JW" has Internal fmax of 64.1 MHz between source register "\P1:CQI[3]" and destination register "\P1:CQI[0]" (period= 15.6 ns)
Info: + Longest register to register delay is 13.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_D51; Fanout = 8; REG Node = '\P1:CQI[3]'
Info: 2: + IC(0.200 ns) + CELL(1.500 ns) = 1.700 ns; Loc. = LC6_D51; Fanout = 1; COMB Node = 'LessThan1~622'
Info: 3: + IC(0.000 ns) + CELL(1.900 ns) = 3.600 ns; Loc. = LC7_D51; Fanout = 1; COMB Node = 'LessThan1~608'
Info: 4: + IC(0.200 ns) + CELL(1.900 ns) = 5.700 ns; Loc. = LC1_D51; Fanout = 1; COMB Node = 'LessThan1~592'
Info: 5: + IC(1.000 ns) + CELL(1.900 ns) = 8.600 ns; Loc. = LC6_D52; Fanout = 2; COMB Node = 'LessThan1~606'
Info: 6: + IC(1.100 ns) + CELL(1.700 ns) = 11.400 ns; Loc. = LC7_D50; Fanout = 8; COMB Node = 'P1~39'
Info: 7: + IC(1.100 ns) + CELL(1.300 ns) = 13.800 ns; Loc. = LC1_D49; Fanout = 7; REG Node = '\P1:CQI[0]'
Info: Total cell delay = 10.200 ns ( 73.91 % )
Info: Total interconnect delay = 3.600 ns ( 26.09 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "JW" to destination register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'JW'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_D49; Fanout = 7; REG Node = '\P1:CQI[0]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: - Longest clock path from clock "JW" to source register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'JW'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_D51; Fanout = 8; REG Node = '\P1:CQI[3]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Micro setup delay of destination is 0.700 ns
Info: tsu for register "\P1:CQI[0]" (data pin = "SZ[0]", clock pin = "JW") is 17.300 ns
Info: + Longest pin to register delay is 18.500 ns
Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_134; Fanout = 1; PIN Node = 'SZ[0]'
Info: 2: + IC(2.900 ns) + CELL(2.000 ns) = 8.300 ns; Loc. = LC7_D51; Fanout = 1; COMB Node = 'LessThan1~608'
Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 10.400 ns; Loc. = LC1_D51; Fanout = 1; COMB Node = 'LessThan1~592'
Info: 4: + IC(1.000 ns) + CELL(1.900 ns) = 13.300 ns; Loc. = LC6_D52; Fanout = 2; COMB Node = 'LessThan1~606'
Info: 5: + IC(1.100 ns) + CELL(1.700 ns) = 16.100 ns; Loc. = LC7_D50; Fanout = 8; COMB Node = 'P1~39'
Info: 6: + IC(1.100 ns) + CELL(1.300 ns) = 18.500 ns; Loc. = LC1_D49; Fanout = 7; REG Node = '\P1:CQI[0]'
Info: Total cell delay = 12.200 ns ( 65.95 % )
Info: Total interconnect delay = 6.300 ns ( 34.05 % )
Info: + Micro setup delay of destination is 0.700 ns
Info: - Shortest clock path from clock "JW" to destination register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'JW'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_D49; Fanout = 7; REG Node = '\P1:CQI[0]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: tco from clock "JW" to destination pin "XSH[0]" through register "\P1:CQI[4]" is 14.600 ns
Info: + Longest clock path from clock "JW" to source register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'JW'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC8_D50; Fanout = 7; REG Node = '\P1:CQI[4]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Longest register to pin delay is 11.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_D50; Fanout = 7; REG Node = '\P1:CQI[4]'
Info: 2: + IC(3.000 ns) + CELL(8.600 ns) = 11.600 ns; Loc. = PIN_44; Fanout = 0; PIN Node = 'XSH[0]'
Info: Total cell delay = 8.600 ns ( 74.14 % )
Info: Total interconnect delay = 3.000 ns ( 25.86 % )
Info: th for register "\P1:CQI[1]" (data pin = "SZ[5]", clock pin = "JW") is -5.100 ns
Info: + Longest clock path from clock "JW" to destination register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'JW'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_D50; Fanout = 6; REG Node = '\P1:CQI[1]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: + Micro hold delay of destination is 0.900 ns
Info: - Shortest pin to register delay is 7.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 2; PIN Node = 'SZ[5]'
Info: 2: + IC(1.400 ns) + CELL(2.000 ns) = 3.900 ns; Loc. = LC6_D52; Fanout = 2; COMB Node = 'LessThan1~606'
Info: 3: + IC(1.100 ns) + CELL(1.700 ns) = 6.700 ns; Loc. = LC7_D50; Fanout = 8; COMB Node = 'P1~39'
Info: 4: + IC(0.200 ns) + CELL(1.000 ns) = 7.900 ns; Loc. = LC5_D50; Fanout = 6; REG Node = '\P1:CQI[1]'
Info: Total cell delay = 5.200 ns ( 65.82 % )
Info: Total interconnect delay = 2.700 ns ( 34.18 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 114 megabytes of memory during processing
Info: Processing ended: Sun Dec 02 20:27:52 2007
Info: Elapsed time: 00:00:08
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