📄 shi.sim.rpt
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; |SHI|P1~39 ; |SHI|P1~39 ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; cout ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; data_out0 ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[4] ; cout ;
; |SHI|CQI~96 ; |SHI|CQI~96 ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ; cout ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; data_out0 ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; data_out0 ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0 ;
; |SHI|LessThan1~592 ; |SHI|LessThan1~592 ; data_out0 ;
; |SHI|LessThan1~606 ; |SHI|LessThan1~606 ; data_out0 ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[3] ; cout ;
; |SHI|LessThan1~602 ; |SHI|LessThan1~602 ; data_out0 ;
; |SHI|LessThan1~607 ; |SHI|LessThan1~620 ; cascout ;
; |SHI|LessThan1~604 ; |SHI|LessThan1~622 ; cascout ;
; |SHI|LessThan1~608 ; |SHI|LessThan1~608 ; data_out0 ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[1] ; cout ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |SHI|JW ; |SHI|JW~corein ; dataout ;
; |SHI|SZ[5] ; |SHI|SZ[5]~corein ; dataout ;
; |SHI|SZ[1] ; |SHI|SZ[1]~corein ; dataout ;
; |SHI|XSL[0] ; |SHI|XSL[0] ; padio ;
; |SHI|XSL[1] ; |SHI|XSL[1] ; padio ;
; |SHI|XSL[2] ; |SHI|XSL[2] ; padio ;
; |SHI|XSL[3] ; |SHI|XSL[3] ; padio ;
; |SHI|XSH[0] ; |SHI|XSH[0] ; padio ;
; |SHI|XSH[1] ; |SHI|XSH[1] ; padio ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
; |SHI|\P1:CQI[6] ; |SHI|\P1:CQI[6] ; data_out0 ;
; |SHI|\P1:CQI[7] ; |SHI|\P1:CQI[7] ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[6] ; cout ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ; cout ;
; |SHI|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7] ; |SHI|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7] ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] ; |SHI|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] ; data_out0 ;
; |SHI|LessThan1~591 ; |SHI|LessThan1~591 ; data_out0 ;
; |SHI|LessThan1~593 ; |SHI|LessThan1~593 ; data_out0 ;
; |SHI|LessThan1~601 ; |SHI|LessThan1~617 ; cascout ;
; |SHI|RST ; |SHI|RST~corein ; dataout ;
; |SHI|SZ[4] ; |SHI|SZ[4]~corein ; dataout ;
; |SHI|SZ[3] ; |SHI|SZ[3]~corein ; dataout ;
; |SHI|SZ[2] ; |SHI|SZ[2]~corein ; dataout ;
; |SHI|SZ[6] ; |SHI|SZ[6]~corein ; dataout ;
; |SHI|SZ[7] ; |SHI|SZ[7]~corein ; dataout ;
; |SHI|SZ[0] ; |SHI|SZ[0]~corein ; dataout ;
; |SHI|XSH[2] ; |SHI|XSH[2] ; padio ;
; |SHI|XSH[3] ; |SHI|XSH[3] ; padio ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
; |SHI|\P1:CQI[6] ; |SHI|\P1:CQI[6] ; data_out0 ;
; |SHI|\P1:CQI[7] ; |SHI|\P1:CQI[7] ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHI|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[6] ; cout ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHI|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ; cout ;
; |SHI|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7] ; |SHI|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7] ; data_out0 ;
; |SHI|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] ; |SHI|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] ; data_out0 ;
; |SHI|LessThan1~591 ; |SHI|LessThan1~591 ; data_out0 ;
; |SHI|LessThan1~593 ; |SHI|LessThan1~593 ; data_out0 ;
; |SHI|LessThan1~601 ; |SHI|LessThan1~617 ; cascout ;
; |SHI|SZ[3] ; |SHI|SZ[3]~corein ; dataout ;
; |SHI|SZ[2] ; |SHI|SZ[2]~corein ; dataout ;
; |SHI|SZ[6] ; |SHI|SZ[6]~corein ; dataout ;
; |SHI|SZ[7] ; |SHI|SZ[7]~corein ; dataout ;
; |SHI|SZ[0] ; |SHI|SZ[0]~corein ; dataout ;
; |SHI|XSH[2] ; |SHI|XSH[2] ; padio ;
; |SHI|XSH[3] ; |SHI|XSH[3] ; padio ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Sun Dec 02 20:32:05 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off SHI -c SHI
Info: Using vector source file "E:/SHI/SHI.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 67.74 %
Info: Number of transitions in simulation is 1738
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 92 megabytes of memory during processing
Info: Processing ended: Sun Dec 02 20:32:18 2007
Info: Elapsed time: 00:00:13
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