prev_cmp_shuzi.qmsg

可预置数字钟

{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "168 " "Info: Allocated 168 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 28 12:39:28 2007 " "Info: Processing ended: Wed Nov 28 12:39:28 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Info: Elapsed time: 00:00:16" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 28 12:39:29 2007 " "Info: Processing started: Wed Nov 28 12:39:29 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off SHUZI -c SHUZI " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off SHUZI -c SHUZI" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 28 12:39:34 2007 " "Info: Processing ended: Wed Nov 28 12:39:34 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 28 12:39:35 2007 " "Info: Processing started: Wed Nov 28 12:39:35 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off SHUZI -c SHUZI " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SHUZI -c SHUZI" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "SM:u7\|Y\[0\] " "Warning: Node \"SM:u7\|Y\[0\]\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SM:u7\|Y\[1\] " "Warning: Node \"SM:u7\|Y\[1\]\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SM:u7\|Y\[2\] " "Warning: Node \"SM:u7\|Y\[2\]\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "JW:u2\|JW2 " "Warning: Node \"JW:u2\|JW2\" is a latch" {  } { { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "JW:u2\|JW1 " "Warning: Node \"JW:u2\|JW1\" is a latch" {  } { { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "JW:u2\|JW3 " "Warning: Node \"JW:u2\|JW3\" is a latch" {  } { { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SM:u7\|CQ\[0\] " "Warning: Node \"SM:u7\|CQ\[0\]\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SM:u7\|CQ\[1\] " "Warning: Node \"SM:u7\|CQ\[1\]\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SM:u7\|CQ\[2\] " "Warning: Node \"SM:u7\|CQ\[2\]\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SM:u7\|CQ\[3\] " "Warning: Node \"SM:u7\|CQ\[3\]\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "GONG " "Info: Assuming node \"GONG\" is an undefined clock" {  } { { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GONG" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK2 " "Info: Assuming node \"CLK2\" is an undefined clock" {  } { { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "DIAO " "Info: Assuming node \"DIAO\" is an undefined clock" {  } { { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DIAO" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "JW:u2\|JW3 " "Info: Detected ripple clock \"JW:u2\|JW3\" as buffer" {  } { { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "JW:u2\|JW3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "JW:u2\|JW1 " "Info: Detected ripple clock \"JW:u2\|JW1\" as buffer" {  } { { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "JW:u2\|JW1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "JW:u2\|JW2 " "Info: Detected ripple clock \"JW:u2\|JW2\" as buffer" {  } { { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "JW:u2\|JW2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "JW:u2\|Mux3~12 " "Info: Detected gated clock \"JW:u2\|Mux3~12\" as buffer" {  } { { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 13 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "JW:u2\|Mux3~12" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "SM:u7\|Mux5~11 " "Info: Detected gated clock \"SM:u7\|Mux5~11\" as buffer" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 20 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SM:u7\|Mux5~11" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "SM:u7\|BT\[1\] " "Info: Detected ripple clock \"SM:u7\|BT\[1\]\" as buffer" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SM:u7\|BT\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "SM:u7\|BT\[2\] " "Info: Detected ripple clock \"SM:u7\|BT\[2\]\" as buffer" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SM:u7\|BT\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ZT:u1\|Z\[0\] " "Info: Detected ripple clock \"ZT:u1\|Z\[0\]\" as buffer" {  } { { "ZT.vhd" "" { Text "E:/SHUZIZHONG/ZT.vhd" 13 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ZT:u1\|Z\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ZT:u1\|Z\[1\] " "Info: Detected ripple clock \"ZT:u1\|Z\[1\]\" as buffer" {  } { { "ZT.vhd" "" { Text "E:/SHUZIZHONG/ZT.vhd" 13 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ZT:u1\|Z\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ZT:u1\|Z\[2\] " "Info: Detected ripple clock \"ZT:u1\|Z\[2\]\" as buffer" {  } { { "ZT.vhd" "" { Text "E:/SHUZIZHONG/ZT.vhd" 13 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ZT:u1\|Z\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "GONG register F_M:u4\|CO register JW:u2\|JW2 31.06 MHz 32.2 ns Internal " "Info: Clock \"GONG\" has Internal fmax of 31.06 MHz between source register \"F_M:u4\|CO\" and destination register \"JW:u2\|JW2\" (period= 32.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.900 ns + Longest register register " "Info: + Longest register to register delay is 4.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns F_M:u4\|CO 1 REG LC1_J28 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_J28; Fanout = 2; REG Node = 'F_M:u4\|CO'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { F_M:u4|CO } "NODE_NAME" } } { "F_M.vhd" "" { Text "E:/SHUZIZHONG/F_M.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 3.000 ns JW:u2\|Mux1~86 2 COMB LC5_J29 1 " "Info: 2: + IC(1.100 ns) + CELL(1.900 ns) = 3.000 ns; Loc. = LC5_J29; Fanout = 1; COMB Node = 'JW:u2\|Mux1~86'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { F_M:u4|CO JW:u2|Mux1~86 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 4.900 ns JW:u2\|JW2 3 REG LC3_J29 9 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.900 ns; Loc. = LC3_J29; Fanout = 9; REG Node = 'JW:u2\|JW2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { JW:u2|Mux1~86 JW:u2|JW2 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 73.47 % ) " "Info: Total cell delay = 3.600 ns ( 73.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 26.53 % ) " "Info: Total interconnect delay = 1.300 ns ( 26.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { F_M:u4|CO JW:u2|Mux1~86 JW:u2|JW2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.900 ns" { F_M:u4|CO JW:u2|Mux1~86 JW:u2|JW2 } { 0.000ns 1.100ns 0.200ns } { 0.000ns 1.900ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.000 ns - Smallest " "Info: - Smallest clock skew is -6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GONG destination 8.600 ns + Shortest register " "Info: + Shortest clock path from clock \"GONG\" to destination register is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns GONG 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'GONG'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GONG } "NODE_NAME" } } { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns ZT:u1\|Z\[1\] 2 REG LC4_J31 8 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC4_J31; Fanout = 8; REG Node = 'ZT:u1\|Z\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { GONG ZT:u1|Z[1] } "NODE_NAME" } } { "ZT.vhd" "" { Text "E:/SHUZIZHONG/ZT.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 4.900 ns JW:u2\|Mux3~12 3 COMB LC5_J31 3 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.900 ns; Loc. = LC5_J31; Fanout = 3; COMB Node = 'JW:u2\|Mux3~12'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { ZT:u1|Z[1] JW:u2|Mux3~12 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(2.000 ns) 8.600 ns JW:u2\|JW2 4 REG LC3_J29 9 " "Info: 4: + IC(1.700 ns) + CELL(2.000 ns) = 8.600 ns; Loc. = LC3_J29; Fanout = 9; REG Node = 'JW:u2\|JW2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { JW:u2|Mux3~12 JW:u2|JW2 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 61.63 % ) " "Info: Total cell delay = 5.300 ns ( 61.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 38.37 % ) " "Info: Total interconnect delay = 3.300 ns ( 38.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.600 ns" { GONG ZT:u1|Z[1] JW:u2|Mux3~12 JW:u2|JW2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.600 ns" { GONG GONG~out ZT:u1|Z[1] JW:u2|Mux3~12 JW:u2|JW2 } { 0.000ns 0.000ns 1.400ns 0.200ns 1.700ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GONG source 14.600 ns - Longest register " "Info: - Longest clock path from clock \"GONG\" to source register is 14.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns GONG 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'GONG'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GONG } "NODE_NAME" } } { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns ZT:u1\|Z\[2\] 2 REG LC2_J31 9 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC2_J31; Fanout = 9; REG Node = 'ZT:u1\|Z\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { GONG ZT:u1|Z[2] } "NODE_NAME" } } { "ZT.vhd" "" { Text "E:/SHUZIZHONG/ZT.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 5.200 ns JW:u2\|Mux3~12 3 COMB LC5_J31 3 " "Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 5.200 ns; Loc. = LC5_J31; Fanout = 3; COMB Node = 'JW:u2\|Mux3~12'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { ZT:u1|Z[2] JW:u2|Mux3~12 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(2.000 ns) 8.900 ns JW:u2\|JW1 4 REG LC1_J29 9 " "Info: 4: + IC(1.700 ns) + CELL(2.000 ns) = 8.900 ns; Loc. = LC1_J29; Fanout = 9; REG Node = 'JW:u2\|JW1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { JW:u2|Mux3~12 JW:u2|JW1 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.700 ns) + CELL(0.000 ns) 14.600 ns F_M:u4\|CO 5 REG LC1_J28 2 " "Info: 5: + IC(5.700 ns) + CELL(0.000 ns) = 14.600 ns; Loc. = LC1_J28; Fanout = 2; REG Node = 'F_M:u4\|CO'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { JW:u2|JW1 F_M:u4|CO } "NODE_NAME" } } { "F_M.vhd" "" { Text "E:/SHUZIZHONG/F_M.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.600 ns ( 38.36 % ) " "Info: Total cell delay = 5.600 ns ( 38.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.000 ns ( 61.64 % ) " "Info: Total interconnect delay = 9.000 ns ( 61.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "14.600 ns" { GONG ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 F_M:u4|CO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "14.600 ns" { GONG GONG~out ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 F_M:u4|CO } { 0.000ns 0.000ns 1.400ns 0.200ns 1.700ns 5.700ns } { 0.000ns 0.500ns 1.100ns 2.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.600 ns" { GONG ZT:u1|Z[1] JW:u2|Mux3~12 JW:u2|JW2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.600 ns" { GONG GONG~out ZT:u1|Z[1] JW:u2|Mux3~12 JW:u2|JW2 } { 0.000ns 0.000ns 1.400ns 0.200ns 1.700ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "14.600 ns" { GONG ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 F_M:u4|CO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "14.600 ns" { GONG GONG~out ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 F_M:u4|CO } { 0.000ns 0.000ns 1.400ns 0.200ns 1.700ns 5.700ns } { 0.000ns 0.500ns 1.100ns 2.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "F_M.vhd" "" { Text "E:/SHUZIZHONG/F_M.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.100 ns + " "Info: + Micro setup delay of destination is 4.100 ns" {  } { { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "F_M.vhd" "" { Text "E:/SHUZIZHONG/F_M.vhd" 7 -1 0 } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { F_M:u4|CO JW:u2|Mux1~86 JW:u2|JW2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.900 ns" { F_M:u4|CO JW:u2|Mux1~86 JW:u2|JW2 } { 0.000ns 1.100ns 0.200ns } { 0.000ns 1.900ns 1.700ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.600 ns" { GONG ZT:u1|Z[1] JW:u2|Mux3~12 JW:u2|JW2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.600 ns" { GONG GONG~out ZT:u1|Z[1] JW:u2|Mux3~12 JW:u2|JW2 } { 0.000ns 0.000ns 1.400ns 0.200ns 1.700ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "14.600 ns" { GONG ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 F_M:u4|CO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "14.600 ns" { GONG GONG~out ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 F_M:u4|CO } { 0.000ns 0.000ns 1.400ns 0.200ns 1.700ns 5.700ns } { 0.000ns 0.500ns 1.100ns 2.000ns 2.000ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK2 register SM:u7\|BT\[1\] register SM:u7\|CQ\[1\] 121.95 MHz 8.2 ns Internal " "Info: Clock \"CLK2\" has Internal fmax of 121.95 MHz between source register \"SM:u7\|BT\[1\]\" and destination register \"SM:u7\|CQ\[1\]\" (period= 8.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.100 ns + Longest register register " "Info: + Longest register to register delay is 9.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SM:u7\|BT\[1\] 1 REG LC4_J49 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_J49; Fanout = 15; REG Node = 'SM:u7\|BT\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SM:u7|BT[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 3.100 ns SM:u7\|Mux1~94 2 COMB LC2_J52 1 " "Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC2_J52; Fanout = 1; COMB Node = 'SM:u7\|Mux1~94'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { SM:u7|BT[1] SM:u7|Mux1~94 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 5.300 ns SM:u7\|Mux1~95 3 COMB LC3_J52 1 " "Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 5.300 ns; Loc. = LC3_J52; Fanout = 1; COMB Node = 'SM:u7\|Mux1~95'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { SM:u7|Mux1~94 SM:u7|Mux1~95 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 7.200 ns SM:u7\|Mux1~97 4 COMB LC8_J52 1 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.200 ns; Loc. = LC8_J52; Fanout = 1; COMB Node = 'SM:u7\|Mux1~97'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { SM:u7|Mux1~95 SM:u7|Mux1~97 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 9.100 ns SM:u7\|CQ\[1\] 5 REG LC7_J52 1 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 9.100 ns; Loc. = LC7_J52; Fanout = 1; REG Node = 'SM:u7\|CQ\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { SM:u7|Mux1~97 SM:u7|CQ[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 81.32 % ) " "Info: Total cell delay = 7.400 ns ( 81.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 18.68 % ) " "Info: Total interconnect delay = 1.700 ns ( 18.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } {