prev_cmp_shuzi.tan.qmsg

可预置数字钟

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ZT:u1\|Z\[2\] JW:u2\|JW1 GONG 1.0 ns " "Info: Found hold time violation between source  pin or register \"ZT:u1\|Z\[2\]\" and destination pin or register \"JW:u2\|JW1\" for clock \"GONG\" (Hold time is 1.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.000 ns + Largest " "Info: + Largest clock skew is 7.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GONG destination 8.900 ns + Longest register " "Info: + Longest clock path from clock \"GONG\" to destination register is 8.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns GONG 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'GONG'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GONG } "NODE_NAME" } } { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns ZT:u1\|Z\[2\] 2 REG LC2_J31 9 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC2_J31; Fanout = 9; REG Node = 'ZT:u1\|Z\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { GONG ZT:u1|Z[2] } "NODE_NAME" } } { "ZT.vhd" "" { Text "E:/SHUZIZHONG/ZT.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 5.200 ns JW:u2\|Mux3~12 3 COMB LC5_J31 3 " "Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 5.200 ns; Loc. = LC5_J31; Fanout = 3; COMB Node = 'JW:u2\|Mux3~12'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { ZT:u1|Z[2] JW:u2|Mux3~12 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(2.000 ns) 8.900 ns JW:u2\|JW1 4 REG LC1_J29 9 " "Info: 4: + IC(1.700 ns) + CELL(2.000 ns) = 8.900 ns; Loc. = LC1_J29; Fanout = 9; REG Node = 'JW:u2\|JW1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { JW:u2|Mux3~12 JW:u2|JW1 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.600 ns ( 62.92 % ) " "Info: Total cell delay = 5.600 ns ( 62.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 37.08 % ) " "Info: Total interconnect delay = 3.300 ns ( 37.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { GONG ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.900 ns" { GONG GONG~out ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 } { 0.000ns 0.000ns 1.400ns 0.200ns 1.700ns } { 0.000ns 0.500ns 1.100ns 2.000ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GONG source 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"GONG\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns GONG 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'GONG'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GONG } "NODE_NAME" } } { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns ZT:u1\|Z\[2\] 2 REG LC2_J31 9 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_J31; Fanout = 9; REG Node = 'ZT:u1\|Z\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { GONG ZT:u1|Z[2] } "NODE_NAME" } } { "ZT.vhd" "" { Text "E:/SHUZIZHONG/ZT.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { GONG ZT:u1|Z[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { GONG GONG~out ZT:u1|Z[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { GONG ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.900 ns" { GONG GONG~out ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 } { 0.000ns 0.000ns 1.400ns 0.200ns 1.700ns } { 0.000ns 0.500ns 1.100ns 2.000ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { GONG ZT:u1|Z[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { GONG GONG~out ZT:u1|Z[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "ZT.vhd" "" { Text "E:/SHUZIZHONG/ZT.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.900 ns - Shortest register register " "Info: - Shortest register to register delay is 4.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ZT:u1\|Z\[2\] 1 REG LC2_J31 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_J31; Fanout = 9; REG Node = 'ZT:u1\|Z\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ZT:u1|Z[2] } "NODE_NAME" } } { "ZT.vhd" "" { Text "E:/SHUZIZHONG/ZT.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 2.100 ns JW:u2\|Mux2~85 2 COMB LC1_J31 1 " "Info: 2: + IC(0.200 ns) + CELL(1.900 ns) = 2.100 ns; Loc. = LC1_J31; Fanout = 1; COMB Node = 'JW:u2\|Mux2~85'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { ZT:u1|Z[2] JW:u2|Mux2~85 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 4.900 ns JW:u2\|JW1 3 REG LC1_J29 9 " "Info: 3: + IC(1.100 ns) + CELL(1.700 ns) = 4.900 ns; Loc. = LC1_J29; Fanout = 9; REG Node = 'JW:u2\|JW1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { JW:u2|Mux2~85 JW:u2|JW1 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 73.47 % ) " "Info: Total cell delay = 3.600 ns ( 73.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 26.53 % ) " "Info: Total interconnect delay = 1.300 ns ( 26.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { ZT:u1|Z[2] JW:u2|Mux2~85 JW:u2|JW1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.900 ns" { ZT:u1|Z[2] JW:u2|Mux2~85 JW:u2|JW1 } { 0.000ns 0.200ns 1.100ns } { 0.000ns 1.900ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "ZT.vhd" "" { Text "E:/SHUZIZHONG/ZT.vhd" 13 -1 0 } } { "JW.vhd" "" { Text "E:/SHUZIZHONG/JW.vhd" 7 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { GONG ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.900 ns" { GONG GONG~out ZT:u1|Z[2] JW:u2|Mux3~12 JW:u2|JW1 } { 0.000ns 0.000ns 1.400ns 0.200ns 1.700ns } { 0.000ns 0.500ns 1.100ns 2.000ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { GONG ZT:u1|Z[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { GONG GONG~out ZT:u1|Z[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { ZT:u1|Z[2] JW:u2|Mux2~85 JW:u2|JW1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.900 ns" { ZT:u1|Z[2] JW:u2|Mux2~85 JW:u2|JW1 } { 0.000ns 0.200ns 1.100ns } { 0.000ns 1.900ns 1.700ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK2 10 " "Warning: Circuit may not operate. Detected 10 non-operational path(s) clocked by clock \"CLK2\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "SM:u7\|BT\[0\] SM:u7\|Y\[0\] CLK2 3.3 ns " "Info: Found hold time violation between source  pin or register \"SM:u7\|BT\[0\]\" and destination pin or register \"SM:u7\|Y\[0\]\" for clock \"CLK2\" (Hold time is 3.3 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.200 ns + Largest " "Info: + Largest clock skew is 7.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 destination 9.100 ns + Longest register " "Info: + Longest clock path from clock \"CLK2\" to destination register is 9.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_183 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns SM:u7\|BT\[1\] 2 REG LC4_J49 15 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC4_J49; Fanout = 15; REG Node = 'SM:u7\|BT\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK2 SM:u7|BT[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 6.000 ns SM:u7\|Mux5~11 3 COMB LC1_J52 7 " "Info: 3: + IC(1.100 ns) + CELL(1.900 ns) = 6.000 ns; Loc. = LC1_J52; Fanout = 7; COMB Node = 'SM:u7\|Mux5~11'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { SM:u7|BT[1] SM:u7|Mux5~11 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 9.100 ns SM:u7\|Y\[0\] 4 REG LC3_J51 1 " "Info: 4: + IC(1.100 ns) + CELL(2.000 ns) = 9.100 ns; Loc. = LC3_J51; Fanout = 1; REG Node = 'SM:u7\|Y\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { SM:u7|Mux5~11 SM:u7|Y[0] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 60.44 % ) " "Info: Total cell delay = 5.500 ns ( 60.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 39.56 % ) " "Info: Total interconnect delay = 3.600 ns ( 39.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.100 ns" { CLK2 SM:u7|BT[1] SM:u7|Mux5~11 SM:u7|Y[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.100 ns" { CLK2 CLK2~out SM:u7|BT[1] SM:u7|Mux5~11 SM:u7|Y[0] } { 0.000ns 0.000ns 1.400ns 1.100ns 1.100ns } { 0.000ns 0.500ns 1.100ns 1.900ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 source 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK2\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_183 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns SM:u7\|BT\[0\] 2 REG LC2_J49 14 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_J49; Fanout = 14; REG Node = 'SM:u7\|BT\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK2 SM:u7|BT[0] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 SM:u7|BT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out SM:u7|BT[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.100 ns" { CLK2 SM:u7|BT[1] SM:u7|Mux5~11 SM:u7|Y[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.100 ns" { CLK2 CLK2~out SM:u7|BT[1] SM:u7|Mux5~11 SM:u7|Y[0] } { 0.000ns 0.000ns 1.400ns 1.100ns 1.100ns } { 0.000ns 0.500ns 1.100ns 1.900ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 SM:u7|BT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out SM:u7|BT[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.800 ns - Shortest register register " "Info: - Shortest register to register delay is 2.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SM:u7\|BT\[0\] 1 REG LC2_J49 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_J49; Fanout = 14; REG Node = 'SM:u7\|BT\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SM:u7|BT[0] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 2.800 ns SM:u7\|Y\[0\] 2 REG LC3_J51 1 " "Info: 2: + IC(1.100 ns) + CELL(1.700 ns) = 2.800 ns; Loc. = LC3_J51; Fanout = 1; REG Node = 'SM:u7\|Y\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { SM:u7|BT[0] SM:u7|Y[0] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.