shuzi.tan.qmsg

可预置数字钟

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK2 register SM:u7\|BT\[1\] register SM:u7\|CQ\[1\] 121.95 MHz 8.2 ns Internal " "Info: Clock \"CLK2\" has Internal fmax of 121.95 MHz between source register \"SM:u7\|BT\[1\]\" and destination register \"SM:u7\|CQ\[1\]\" (period= 8.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.100 ns + Longest register register " "Info: + Longest register to register delay is 9.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SM:u7\|BT\[1\] 1 REG LC4_J49 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_J49; Fanout = 15; REG Node = 'SM:u7\|BT\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SM:u7|BT[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 3.100 ns SM:u7\|Mux1~94 2 COMB LC2_J52 1 " "Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC2_J52; Fanout = 1; COMB Node = 'SM:u7\|Mux1~94'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { SM:u7|BT[1] SM:u7|Mux1~94 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 5.300 ns SM:u7\|Mux1~95 3 COMB LC3_J52 1 " "Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 5.300 ns; Loc. = LC3_J52; Fanout = 1; COMB Node = 'SM:u7\|Mux1~95'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { SM:u7|Mux1~94 SM:u7|Mux1~95 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 7.200 ns SM:u7\|Mux1~97 4 COMB LC8_J52 1 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.200 ns; Loc. = LC8_J52; Fanout = 1; COMB Node = 'SM:u7\|Mux1~97'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { SM:u7|Mux1~95 SM:u7|Mux1~97 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 9.100 ns SM:u7\|CQ\[1\] 5 REG LC7_J52 1 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 9.100 ns; Loc. = LC7_J52; Fanout = 1; REG Node = 'SM:u7\|CQ\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { SM:u7|Mux1~97 SM:u7|CQ[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 81.32 % ) " "Info: Total cell delay = 7.400 ns ( 81.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 18.68 % ) " "Info: Total interconnect delay = 1.700 ns ( 18.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.100 ns" { SM:u7|BT[1] SM:u7|Mux1~94 SM:u7|Mux1~95 SM:u7|Mux1~97 SM:u7|CQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.100 ns" { SM:u7|BT[1] SM:u7|Mux1~94 SM:u7|Mux1~95 SM:u7|Mux1~97 SM:u7|CQ[1] } { 0.000ns 1.100ns 0.200ns 0.200ns 0.200ns } { 0.000ns 2.000ns 2.000ns 1.700ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.100 ns - Smallest " "Info: - Smallest clock skew is 6.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 destination 8.000 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK2\" to destination register is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_183 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns SM:u7\|BT\[2\] 2 REG LC5_J49 9 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC5_J49; Fanout = 9; REG Node = 'SM:u7\|BT\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK2 SM:u7|BT[2] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 5.800 ns SM:u7\|Mux5~11 3 COMB LC1_J52 7 " "Info: 3: + IC(1.100 ns) + CELL(1.700 ns) = 5.800 ns; Loc. = LC1_J52; Fanout = 7; COMB Node = 'SM:u7\|Mux5~11'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { SM:u7|BT[2] SM:u7|Mux5~11 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 8.000 ns SM:u7\|CQ\[1\] 4 REG LC7_J52 1 " "Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 8.000 ns; Loc. = LC7_J52; Fanout = 1; REG Node = 'SM:u7\|CQ\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { SM:u7|Mux5~11 SM:u7|CQ[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 66.25 % ) " "Info: Total cell delay = 5.300 ns ( 66.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 33.75 % ) " "Info: Total interconnect delay = 2.700 ns ( 33.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CLK2 SM:u7|BT[2] SM:u7|Mux5~11 SM:u7|CQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { CLK2 CLK2~out SM:u7|BT[2] SM:u7|Mux5~11 SM:u7|CQ[1] } { 0.000ns 0.000ns 1.400ns 1.100ns 0.200ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"CLK2\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_183 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns SM:u7\|BT\[1\] 2 REG LC4_J49 15 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_J49; Fanout = 15; REG Node = 'SM:u7\|BT\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK2 SM:u7|BT[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 SM:u7|BT[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out SM:u7|BT[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CLK2 SM:u7|BT[2] SM:u7|Mux5~11 SM:u7|CQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { CLK2 CLK2~out SM:u7|BT[2] SM:u7|Mux5~11 SM:u7|CQ[1] } { 0.000ns 0.000ns 1.400ns 1.100ns 0.200ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 SM:u7|BT[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out SM:u7|BT[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.100 ns + " "Info: + Micro setup delay of destination is 4.100 ns" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.100 ns" { SM:u7|BT[1] SM:u7|Mux1~94 SM:u7|Mux1~95 SM:u7|Mux1~97 SM:u7|CQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.100 ns" { SM:u7|BT[1] SM:u7|Mux1~94 SM:u7|Mux1~95 SM:u7|Mux1~97 SM:u7|CQ[1] } { 0.000ns 1.100ns 0.200ns 0.200ns 0.200ns } { 0.000ns 2.000ns 2.000ns 1.700ns 1.700ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CLK2 SM:u7|BT[2] SM:u7|Mux5~11 SM:u7|CQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { CLK2 CLK2~out SM:u7|BT[2] SM:u7|Mux5~11 SM:u7|CQ[1] } { 0.000ns 0.000ns 1.400ns 1.100ns 0.200ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 SM:u7|BT[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out SM:u7|BT[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "DIAO register register SHIZHI:u3\|SZI SHIZHI:u3\|SZI 200.0 MHz Internal " "Info: Clock \"DIAO\" Internal fmax is restricted to 200.0 MHz between source register \"SHIZHI:u3\|SZI\" and destination register \"SHIZHI:u3\|SZI\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.200 ns + Longest register register " "Info: + Longest register to register delay is 1.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SHIZHI:u3\|SZI 1 REG LC4_H4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_H4; Fanout = 3; REG Node = 'SHIZHI:u3\|SZI'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SHIZHI:u3|SZI } "NODE_NAME" } } { "SHIZHI.vhd" "" { Text "E:/SHUZIZHONG/SHIZHI.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 1.200 ns SHIZHI:u3\|SZI 2 REG LC4_H4 3 " "Info: 2: + IC(0.200 ns) + CELL(1.000 ns) = 1.200 ns; Loc. = LC4_H4; Fanout = 3; REG Node = 'SHIZHI:u3\|SZI'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { SHIZHI:u3|SZI SHIZHI:u3|SZI } "NODE_NAME" } } { "SHIZHI.vhd" "" { Text "E:/SHUZIZHONG/SHIZHI.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.000 ns ( 83.33 % ) " "Info: Total cell delay = 1.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.200 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { SHIZHI:u3|SZI SHIZHI:u3|SZI } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.200 ns" { SHIZHI:u3|SZI SHIZHI:u3|SZI } { 0.000ns 0.200ns } { 0.000ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DIAO destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"DIAO\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DIAO 1 CLK PIN_182 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 4; CLK Node = 'DIAO'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DIAO } "NODE_NAME" } } { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns SHIZHI:u3\|SZI 2 REG LC4_H4 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_H4; Fanout = 3; REG Node = 'SHIZHI:u3\|SZI'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { DIAO SHIZHI:u3|SZI } "NODE_NAME" } } { "SHIZHI.vhd" "" { Text "E:/SHUZIZHONG/SHIZHI.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { DIAO SHIZHI:u3|SZI } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { DIAO DIAO~out SHIZHI:u3|SZI } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DIAO source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"DIAO\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DIAO 1 CLK PIN_182 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 4; CLK Node = 'DIAO'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DIAO } "NODE_NAME" } } { "SHUZI.vhd" "" { Text "E:/SHUZIZHONG/SHUZI.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns SHIZHI:u3\|SZI 2 REG LC4_H4 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_H4; Fanout = 3; REG Node = 'SHIZHI:u3\|SZI'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { DIAO SHIZHI:u3|SZI } "NODE_NAME" } } { "SHIZHI.vhd" "" { Text "E:/SHUZIZHONG/SHIZHI.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { DIAO SHIZHI:u3|SZI } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { DIAO DIAO~out SHIZHI:u3|SZI } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { DIAO SHIZHI:u3|SZI } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { DIAO DIAO~out SHIZHI:u3|SZI } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { DIAO SHIZHI:u3|SZI } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { DIAO DIAO~out SHIZHI:u3|SZI } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "SHIZHI.vhd" "" { Text "E:/SHUZIZHONG/SHIZHI.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "SHIZHI.vhd" "" { Text "E:/SHUZIZHONG/SHIZHI.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { SHIZHI:u3|SZI SHIZHI:u3|SZI } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.200 ns" { SHIZHI:u3|SZI SHIZHI:u3|SZI } { 0.000ns 0.200ns } { 0.000ns 1.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { DIAO SHIZHI:u3|SZI } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { DIAO DIAO~out SHIZHI:u3|SZI } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { DIAO SHIZHI:u3|SZI } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { DIAO DIAO~out SHIZHI:u3|SZI } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SHIZHI:u3|SZI } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { SHIZHI:u3|SZI } {  } {  } "" } } { "SHIZHI.vhd" "" { Text "E:/SHUZIZHONG/SHIZHI.vhd" 12 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "GONG 4 " "Warning: Circuit may not operate. Detected 4 non-operational path(s) clocked by clock \"GONG\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}