📄 f_m.sim.rpt
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+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
; |F_M|CQI[0] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |F_M|CQI[1] ; |F_M|CQI[1] ; data_out0 ;
; |F_M|CQI[2] ; |F_M|CQI[2] ; data_out0 ;
; |F_M|CQI[3] ; |F_M|CQI[3] ; data_out0 ;
; |F_M|CQI[4] ; |F_M|CQI[4] ; data_out0 ;
; |F_M|CQI[5] ; |F_M|CQI[5] ; data_out0 ;
; |F_M|CQI[6] ; |F_M|CQI[6] ; data_out0 ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; data_out0 ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; cout ;
; |F_M|LessThan1~129 ; |F_M|LessThan1~129 ; data_out0 ;
; |F_M|LessThan1~130 ; |F_M|LessThan1~130 ; data_out0 ;
; |F_M|process0~63 ; |F_M|process0~63 ; data_out0 ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; data_out0 ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; data_out0 ;
; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; data_out0 ;
; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[4] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; data_out0 ;
; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; data_out0 ;
; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; data_out0 ;
; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0 ;
; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[6] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0 ;
; |F_M|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7] ; |F_M|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7] ; data_out0 ;
; |F_M|Equal1~59 ; |F_M|Equal1~65 ; cascout ;
; |F_M|CQI~569 ; |F_M|CQI~569 ; data_out0 ;
; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[3] ; cout ;
; |F_M|CQI~568 ; |F_M|CQI~581 ; cascout ;
; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[1] ; cout ;
; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |F_M|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |F_M|Equal1~61 ; |F_M|Equal1~61 ; data_out0 ;
; |F_M|JW ; |F_M|JW~corein ; dataout ;
; |F_M|FM[0] ; |F_M|FM[0] ; padio ;
; |F_M|FM[1] ; |F_M|FM[1] ; padio ;
; |F_M|FM[2] ; |F_M|FM[2] ; padio ;
; |F_M|FM[3] ; |F_M|FM[3] ; padio ;
; |F_M|FM[4] ; |F_M|FM[4] ; padio ;
; |F_M|FM[5] ; |F_M|FM[5] ; padio ;
; |F_M|FM[6] ; |F_M|FM[6] ; padio ;
; |F_M|CO ; |F_M|CO ; padio ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+--------------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; |F_M|CQI[7] ; |F_M|CQI[7] ; data_out0 ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] ; |F_M|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] ; data_out0 ;
; |F_M|RST ; |F_M|RST~corein ; dataout ;
; |F_M|FM[7] ; |F_M|FM[7] ; padio ;
+--------------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+--------------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; |F_M|CQI[7] ; |F_M|CQI[7] ; data_out0 ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |F_M|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ; cout ;
; |F_M|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] ; |F_M|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7] ; data_out0 ;
; |F_M|FM[7] ; |F_M|FM[7] ; padio ;
+--------------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Tue Nov 27 19:08:01 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off F_M -c F_M
Info: Using vector source file "E:/F_M/F_M.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 84.00 %
Info: Number of transitions in simulation is 1528
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 92 megabytes of memory during processing
Info: Processing ended: Tue Nov 27 19:08:02 2007
Info: Elapsed time: 00:00:01
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