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; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|F_M:u4|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; |SHUZI|F_M:u4|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|F_M:u5|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; |SHUZI|F_M:u5|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|SHI:u6|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; |SHUZI|SHI:u6|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|RST                                                                        ; |SHUZI|RST~corein                                                                 ; dataout          ;
+-----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                                                 ;
+-----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
; Node Name                                                                         ; Output Port Name                                                                  ; Output Port Type ;
+-----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
; |SHUZI|F_M:u4|CQI[5]                                                              ; |SHUZI|F_M:u4|CQI[5]                                                              ; data_out0        ;
; |SHUZI|F_M:u5|CQI[5]                                                              ; |SHUZI|F_M:u5|CQI[5]                                                              ; data_out0        ;
; |SHUZI|SHI:u6|\P1:CQI[5]                                                          ; |SHUZI|SHI:u6|\P1:CQI[5]                                                          ; data_out0        ;
; |SHUZI|F_M:u4|CQI[6]                                                              ; |SHUZI|F_M:u4|CQI[6]                                                              ; data_out0        ;
; |SHUZI|F_M:u5|CQI[6]                                                              ; |SHUZI|F_M:u5|CQI[6]                                                              ; data_out0        ;
; |SHUZI|SHI:u6|\P1:CQI[6]                                                          ; |SHUZI|SHI:u6|\P1:CQI[6]                                                          ; data_out0        ;
; |SHUZI|F_M:u4|CQI[7]                                                              ; |SHUZI|F_M:u4|CQI[7]                                                              ; data_out0        ;
; |SHUZI|F_M:u5|CQI[7]                                                              ; |SHUZI|F_M:u5|CQI[7]                                                              ; data_out0        ;
; |SHUZI|SHI:u6|\P1:CQI[7]                                                          ; |SHUZI|SHI:u6|\P1:CQI[7]                                                          ; data_out0        ;
; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4]      ; cout             ;
; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4]      ; cout             ;
; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4]      ; cout             ;
; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; data_out0        ;
; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5]      ; cout             ;
; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; data_out0        ;
; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5]      ; cout             ;
; |SHUZI|SHI:u6|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHUZI|SHI:u6|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[5]      ; cout             ;
; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; data_out0        ;
; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5]      ; cout             ;
; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0        ;
; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6]      ; cout             ;
; |SHUZI|F_M:u4|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHUZI|F_M:u4|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[6]      ; cout             ;
; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0        ;
; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6]      ; cout             ;
; |SHUZI|F_M:u5|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHUZI|F_M:u5|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[6]      ; cout             ;
; |SHUZI|SHI:u6|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHUZI|SHI:u6|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0        ;
; |SHUZI|SHI:u6|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHUZI|SHI:u6|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[6]      ; cout             ;
; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0        ;
; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6]      ; cout             ;
; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3]      ; cout             ;
; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3]      ; cout             ;
; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3]      ; cout             ;
; |SHUZI|JW:u2|Mux3~12                                                              ; |SHUZI|JW:u2|Mux3~12                                                              ; data_out0        ;
; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; |SHUZI|F_M:u4|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|F_M:u4|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; |SHUZI|F_M:u4|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; |SHUZI|F_M:u5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|F_M:u5|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; |SHUZI|F_M:u5|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|SHI:u6|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; |SHUZI|SHI:u6|lpm_add_sub:Add1|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; |SHUZI|SHI:u6|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                    ; data_out0        ;
; |SHUZI|F_M:u4|CO~88                                                               ; |SHUZI|F_M:u4|CO~88                                                               ; data_out0        ;
+-----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Nov 28 12:47:19 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off SHUZI -c SHUZI
Info: Using vector source file "E:/SHUZIZHONG/SHUZI.vwf"
Info: Inverted registers were found during simulation
    Info: Register: |SHUZI|SHIZHI:u3|SZI
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      74.53 %
Info: Number of transitions in simulation is 4126
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 93 megabytes of memory during processing
    Info: Processing ended: Wed Nov 28 12:47:21 2007
    Info: Elapsed time: 00:00:02
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