sm.tan.qmsg

可预置数字钟

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK2 CQ\[3\] CQ\[3\]\$latch 21.600 ns register " "Info: tco from clock \"CLK2\" to destination pin \"CQ\[3\]\" through register \"CQ\[3\]\$latch\" is 21.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 source 9.800 ns + Longest register " "Info: + Longest clock path from clock \"CLK2\" to source register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns BT\[1\] 2 REG LC1_A4 15 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_A4; Fanout = 15; REG Node = 'BT\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK2 BT[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 6.000 ns Mux5~11 3 COMB LC4_A5 7 " "Info: 3: + IC(1.100 ns) + CELL(1.900 ns) = 6.000 ns; Loc. = LC4_A5; Fanout = 7; COMB Node = 'Mux5~11'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { BT[1] Mux5~11 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.000 ns) 9.800 ns CQ\[3\]\$latch 4 REG LC5_A3 1 " "Info: 4: + IC(1.800 ns) + CELL(2.000 ns) = 9.800 ns; Loc. = LC5_A3; Fanout = 1; REG Node = 'CQ\[3\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { Mux5~11 CQ[3]$latch } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 56.12 % ) " "Info: Total cell delay = 5.500 ns ( 56.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 43.88 % ) " "Info: Total interconnect delay = 4.300 ns ( 43.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK2 BT[1] Mux5~11 CQ[3]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK2 CLK2~out BT[1] Mux5~11 CQ[3]$latch } { 0.000ns 0.000ns 1.400ns 1.100ns 1.800ns } { 0.000ns 0.500ns 1.100ns 1.900ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.800 ns + Longest register pin " "Info: + Longest register to pin delay is 11.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CQ\[3\]\$latch 1 REG LC5_A3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A3; Fanout = 1; REG Node = 'CQ\[3\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CQ[3]$latch } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(8.600 ns) 11.800 ns CQ\[3\] 2 PIN PIN_113 0 " "Info: 2: + IC(3.200 ns) + CELL(8.600 ns) = 11.800 ns; Loc. = PIN_113; Fanout = 0; PIN Node = 'CQ\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.800 ns" { CQ[3]$latch CQ[3] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns ( 72.88 % ) " "Info: Total cell delay = 8.600 ns ( 72.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 27.12 % ) " "Info: Total interconnect delay = 3.200 ns ( 27.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.800 ns" { CQ[3]$latch CQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.800 ns" { CQ[3]$latch CQ[3] } { 0.000ns 3.200ns } { 0.000ns 8.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK2 BT[1] Mux5~11 CQ[3]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK2 CLK2~out BT[1] Mux5~11 CQ[3]$latch } { 0.000ns 0.000ns 1.400ns 1.100ns 1.800ns } { 0.000ns 0.500ns 1.100ns 1.900ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.800 ns" { CQ[3]$latch CQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.800 ns" { CQ[3]$latch CQ[3] } { 0.000ns 3.200ns } { 0.000ns 8.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "CQ\[0\]\$latch SHI\[4\] CLK2 2.300 ns register " "Info: th for register \"CQ\[0\]\$latch\" (data pin = \"SHI\[4\]\", clock pin = \"CLK2\") is 2.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 destination 9.800 ns + Longest register " "Info: + Longest clock path from clock \"CLK2\" to destination register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns BT\[1\] 2 REG LC1_A4 15 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_A4; Fanout = 15; REG Node = 'BT\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK2 BT[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 6.000 ns Mux5~11 3 COMB LC4_A5 7 " "Info: 3: + IC(1.100 ns) + CELL(1.900 ns) = 6.000 ns; Loc. = LC4_A5; Fanout = 7; COMB Node = 'Mux5~11'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { BT[1] Mux5~11 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.000 ns) 9.800 ns CQ\[0\]\$latch 4 REG LC7_A2 1 " "Info: 4: + IC(1.800 ns) + CELL(2.000 ns) = 9.800 ns; Loc. = LC7_A2; Fanout = 1; REG Node = 'CQ\[0\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { Mux5~11 CQ[0]$latch } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 56.12 % ) " "Info: Total cell delay = 5.500 ns ( 56.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 43.88 % ) " "Info: Total interconnect delay = 4.300 ns ( 43.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK2 BT[1] Mux5~11 CQ[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK2 CLK2~out BT[1] Mux5~11 CQ[0]$latch } { 0.000ns 0.000ns 1.400ns 1.100ns 1.800ns } { 0.000ns 0.500ns 1.100ns 1.900ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SHI\[4\] 1 PIN PIN_183 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 1; PIN Node = 'SHI\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SHI[4] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.700 ns) 3.500 ns Mux0~97 2 COMB LC1_A2 1 " "Info: 2: + IC(1.300 ns) + CELL(1.700 ns) = 3.500 ns; Loc. = LC1_A2; Fanout = 1; COMB Node = 'Mux0~97'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { SHI[4] Mux0~97 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 5.600 ns Mux0~98 3 COMB LC2_A2 1 " "Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 5.600 ns; Loc. = LC2_A2; Fanout = 1; COMB Node = 'Mux0~98'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { Mux0~97 Mux0~98 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 7.500 ns CQ\[0\]\$latch 4 REG LC7_A2 1 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.500 ns; Loc. = LC7_A2; Fanout = 1; REG Node = 'CQ\[0\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { Mux0~98 CQ[0]$latch } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns ( 77.33 % ) " "Info: Total cell delay = 5.800 ns ( 77.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 22.67 % ) " "Info: Total interconnect delay = 1.700 ns ( 22.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { SHI[4] Mux0~97 Mux0~98 CQ[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.500 ns" { SHI[4] SHI[4]~out Mux0~97 Mux0~98 CQ[0]$latch } { 0.000ns 0.000ns 1.300ns 0.200ns 0.200ns } { 0.000ns 0.500ns 1.700ns 1.900ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK2 BT[1] Mux5~11 CQ[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK2 CLK2~out BT[1] Mux5~11 CQ[0]$latch } { 0.000ns 0.000ns 1.400ns 1.100ns 1.800ns } { 0.000ns 0.500ns 1.100ns 1.900ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { SHI[4] Mux0~97 Mux0~98 CQ[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.500 ns" { SHI[4] SHI[4]~out Mux0~97 Mux0~98 CQ[0]$latch } { 0.000ns 0.000ns 1.300ns 0.200ns 0.200ns } { 0.000ns 0.500ns 1.700ns 1.900ns 1.700ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 27 20:57:57 2007 " "Info: Processing ended: Tue Nov 27 20:57:57 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}