sm.tan.qmsg

可预置数字钟

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK2 register BT\[1\] register CQ\[1\]\$latch 111.11 MHz 9.0 ns Internal " "Info: Clock \"CLK2\" has Internal fmax of 111.11 MHz between source register \"BT\[1\]\" and destination register \"CQ\[1\]\$latch\" (period= 9.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BT\[1\] 1 REG LC1_A4 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A4; Fanout = 15; REG Node = 'BT\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { BT[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 2.200 ns Mux1~94 2 COMB LC3_A4 1 " "Info: 2: + IC(0.200 ns) + CELL(2.000 ns) = 2.200 ns; Loc. = LC3_A4; Fanout = 1; COMB Node = 'Mux1~94'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { BT[1] Mux1~94 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.000 ns) 5.200 ns Mux1~95 3 COMB LC5_A5 1 " "Info: 3: + IC(1.000 ns) + CELL(2.000 ns) = 5.200 ns; Loc. = LC5_A5; Fanout = 1; COMB Node = 'Mux1~95'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { Mux1~94 Mux1~95 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 7.100 ns Mux1~97 4 COMB LC8_A5 1 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.100 ns; Loc. = LC8_A5; Fanout = 1; COMB Node = 'Mux1~97'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { Mux1~95 Mux1~97 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 9.000 ns CQ\[1\]\$latch 5 REG LC6_A5 1 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 9.000 ns; Loc. = LC6_A5; Fanout = 1; REG Node = 'CQ\[1\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { Mux1~97 CQ[1]$latch } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 82.22 % ) " "Info: Total cell delay = 7.400 ns ( 82.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 17.78 % ) " "Info: Total interconnect delay = 1.600 ns ( 17.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { BT[1] Mux1~94 Mux1~95 Mux1~97 CQ[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.000 ns" { BT[1] Mux1~94 Mux1~95 Mux1~97 CQ[1]$latch } { 0.000ns 0.200ns 1.000ns 0.200ns 0.200ns } { 0.000ns 2.000ns 2.000ns 1.700ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.200 ns - Smallest " "Info: - Smallest clock skew is 5.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 destination 7.100 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK2\" to destination register is 7.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns BT\[2\] 2 REG LC3_A5 9 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC3_A5; Fanout = 9; REG Node = 'BT\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK2 BT[2] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 4.900 ns Mux5~11 3 COMB LC4_A5 7 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.900 ns; Loc. = LC4_A5; Fanout = 7; COMB Node = 'Mux5~11'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { BT[2] Mux5~11 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 7.100 ns CQ\[1\]\$latch 4 REG LC6_A5 1 " "Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 7.100 ns; Loc. = LC6_A5; Fanout = 1; REG Node = 'CQ\[1\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { Mux5~11 CQ[1]$latch } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 74.65 % ) " "Info: Total cell delay = 5.300 ns ( 74.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 25.35 % ) " "Info: Total interconnect delay = 1.800 ns ( 25.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.100 ns" { CLK2 BT[2] Mux5~11 CQ[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.100 ns" { CLK2 CLK2~out BT[2] Mux5~11 CQ[1]$latch } { 0.000ns 0.000ns 1.400ns 0.200ns 0.200ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"CLK2\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns BT\[1\] 2 REG LC1_A4 15 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_A4; Fanout = 15; REG Node = 'BT\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK2 BT[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 BT[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out BT[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.100 ns" { CLK2 BT[2] Mux5~11 CQ[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.100 ns" { CLK2 CLK2~out BT[2] Mux5~11 CQ[1]$latch } { 0.000ns 0.000ns 1.400ns 0.200ns 0.200ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 BT[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out BT[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.100 ns + " "Info: + Micro setup delay of destination is 4.100 ns" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { BT[1] Mux1~94 Mux1~95 Mux1~97 CQ[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.000 ns" { BT[1] Mux1~94 Mux1~95 Mux1~97 CQ[1]$latch } { 0.000ns 0.200ns 1.000ns 0.200ns 0.200ns } { 0.000ns 2.000ns 2.000ns 1.700ns 1.700ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.100 ns" { CLK2 BT[2] Mux5~11 CQ[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.100 ns" { CLK2 CLK2~out BT[2] Mux5~11 CQ[1]$latch } { 0.000ns 0.000ns 1.400ns 0.200ns 0.200ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 BT[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out BT[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK2 12 " "Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock \"CLK2\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "BT\[0\] Y\[0\]\$latch CLK2 4.0 ns " "Info: Found hold time violation between source  pin or register \"BT\[0\]\" and destination pin or register \"Y\[0\]\$latch\" for clock \"CLK2\" (Hold time is 4.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.900 ns + Largest " "Info: + Largest clock skew is 7.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 destination 9.800 ns + Longest register " "Info: + Longest clock path from clock \"CLK2\" to destination register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns BT\[1\] 2 REG LC1_A4 15 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_A4; Fanout = 15; REG Node = 'BT\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK2 BT[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 6.000 ns Mux5~11 3 COMB LC4_A5 7 " "Info: 3: + IC(1.100 ns) + CELL(1.900 ns) = 6.000 ns; Loc. = LC4_A5; Fanout = 7; COMB Node = 'Mux5~11'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { BT[1] Mux5~11 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.000 ns) 9.800 ns Y\[0\]\$latch 4 REG LC6_A2 1 " "Info: 4: + IC(1.800 ns) + CELL(2.000 ns) = 9.800 ns; Loc. = LC6_A2; Fanout = 1; REG Node = 'Y\[0\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { Mux5~11 Y[0]$latch } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 56.12 % ) " "Info: Total cell delay = 5.500 ns ( 56.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 43.88 % ) " "Info: Total interconnect delay = 4.300 ns ( 43.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK2 BT[1] Mux5~11 Y[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK2 CLK2~out BT[1] Mux5~11 Y[0]$latch } { 0.000ns 0.000ns 1.400ns 1.100ns 1.800ns } { 0.000ns 0.500ns 1.100ns 1.900ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 source 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK2\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns BT\[0\] 2 REG LC2_A4 14 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_A4; Fanout = 14; REG Node = 'BT\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK2 BT[0] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 BT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out BT[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK2 BT[1] Mux5~11 Y[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK2 CLK2~out BT[1] Mux5~11 Y[0]$latch } { 0.000ns 0.000ns 1.400ns 1.100ns 1.800ns } { 0.000ns 0.500ns 1.100ns 1.900ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 BT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out BT[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.800 ns - Shortest register register " "Info: - Shortest register to register delay is 2.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BT\[0\] 1 REG LC2_A4 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A4; Fanout = 14; REG Node = 'BT\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { BT[0] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 2.800 ns Y\[0\]\$latch 2 REG LC6_A2 1 " "Info: 2: + IC(1.100 ns) + CELL(1.700 ns) = 2.800 ns; Loc. = LC6_A2; Fanout = 1; REG Node = 'Y\[0\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { BT[0] Y[0]$latch } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns ( 60.71 % ) " "Info: Total cell delay = 1.700 ns ( 60.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns ( 39.29 % ) " "Info: Total interconnect delay = 1.100 ns ( 39.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { BT[0] Y[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.800 ns" { BT[0] Y[0]$latch } { 0.000ns 1.100ns } { 0.000ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { CLK2 BT[1] Mux5~11 Y[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.800 ns" { CLK2 CLK2~out BT[1] Mux5~11 Y[0]$latch } { 0.000ns 0.000ns 1.400ns 1.100ns 1.800ns } { 0.000ns 0.500ns 1.100ns 1.900ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK2 BT[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK2 CLK2~out BT[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { BT[0] Y[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.800 ns" { BT[0] Y[0]$latch } { 0.000ns 1.100ns } { 0.000ns 1.700ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "CQ\[1\]\$latch FEN\[1\] CLK2 12.600 ns register " "Info: tsu for register \"CQ\[1\]\$latch\" (data pin = \"FEN\[1\]\", clock pin = \"CLK2\") is 12.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.600 ns + Longest pin register " "Info: + Longest pin to register delay is 15.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns FEN\[1\] 1 PIN PIN_173 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_173; Fanout = 1; PIN Node = 'FEN\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FEN[1] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(1.900 ns) 8.800 ns Mux1~94 2 COMB LC3_A4 1 " "Info: 2: + IC(3.800 ns) + CELL(1.900 ns) = 8.800 ns; Loc. = LC3_A4; Fanout = 1; COMB Node = 'Mux1~94'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { FEN[1] Mux1~94 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.000 ns) 11.800 ns Mux1~95 3 COMB LC5_A5 1 " "Info: 3: + IC(1.000 ns) + CELL(2.000 ns) = 11.800 ns; Loc. = LC5_A5; Fanout = 1; COMB Node = 'Mux1~95'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { Mux1~94 Mux1~95 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 13.700 ns Mux1~97 4 COMB LC8_A5 1 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 13.700 ns; Loc. = LC8_A5; Fanout = 1; COMB Node = 'Mux1~97'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { Mux1~95 Mux1~97 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 15.600 ns CQ\[1\]\$latch 5 REG LC6_A5 1 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 15.600 ns; Loc. = LC6_A5; Fanout = 1; REG Node = 'CQ\[1\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { Mux1~97 CQ[1]$latch } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.400 ns ( 66.67 % ) " "Info: Total cell delay = 10.400 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns ( 33.33 % ) " "Info: Total interconnect delay = 5.200 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "15.600 ns" { FEN[1] Mux1~94 Mux1~95 Mux1~97 CQ[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "15.600 ns" { FEN[1] FEN[1]~out Mux1~94 Mux1~95 Mux1~97 CQ[1]$latch } { 0.000ns 0.000ns 3.800ns 1.000ns 0.200ns 0.200ns } { 0.000ns 3.100ns 1.900ns 2.000ns 1.700ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.100 ns + " "Info: + Micro setup delay of destination is 4.100 ns" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 destination 7.100 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK2\" to destination register is 7.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK2 1 CLK PIN_79 3 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns BT\[2\] 2 REG LC3_A5 9 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC3_A5; Fanout = 9; REG Node = 'BT\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK2 BT[2] } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 4.900 ns Mux5~11 3 COMB LC4_A5 7 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.900 ns; Loc. = LC4_A5; Fanout = 7; COMB Node = 'Mux5~11'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { BT[2] Mux5~11 } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 7.100 ns CQ\[1\]\$latch 4 REG LC6_A5 1 " "Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 7.100 ns; Loc. = LC6_A5; Fanout = 1; REG Node = 'CQ\[1\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { Mux5~11 CQ[1]$latch } "NODE_NAME" } } { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 74.65 % ) " "Info: Total cell delay = 5.300 ns ( 74.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 25.35 % ) " "Info: Total interconnect delay = 1.800 ns ( 25.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.100 ns" { CLK2 BT[2] Mux5~11 CQ[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.100 ns" { CLK2 CLK2~out BT[2] Mux5~11 CQ[1]$latch } { 0.000ns 0.000ns 1.400ns 0.200ns 0.200ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "15.600 ns" { FEN[1] Mux1~94 Mux1~95 Mux1~97 CQ[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "15.600 ns" { FEN[1] FEN[1]~out Mux1~94 Mux1~95 Mux1~97 CQ[1]$latch } { 0.000ns 0.000ns 3.800ns 1.000ns 0.200ns 0.200ns } { 0.000ns 3.100ns 1.900ns 2.000ns 1.700ns 1.700ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.100 ns" { CLK2 BT[2] Mux5~11 CQ[1]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.100 ns" { CLK2 CLK2~out BT[2] Mux5~11 CQ[1]$latch } { 0.000ns 0.000ns 1.400ns 0.200ns 0.200ns } { 0.000ns 0.500ns 1.100ns 1.700ns 2.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}