sm.tan.rpt

可预置数字钟

    Warning: Node "Y[0]$latch" is a latch
    Warning: Node "Y[1]$latch" is a latch
    Warning: Node "Y[2]$latch" is a latch
    Warning: Node "CQ[0]$latch" is a latch
    Warning: Node "CQ[1]$latch" is a latch
    Warning: Node "CQ[2]$latch" is a latch
    Warning: Node "CQ[3]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK2" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "Mux5~11" as buffer
    Info: Detected ripple clock "BT[1]" as buffer
    Info: Detected ripple clock "BT[2]" as buffer
Info: Clock "CLK2" has Internal fmax of 111.11 MHz between source register "BT[1]" and destination register "CQ[1]$latch" (period= 9.0 ns)
    Info: + Longest register to register delay is 9.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A4; Fanout = 15; REG Node = 'BT[1]'
        Info: 2: + IC(0.200 ns) + CELL(2.000 ns) = 2.200 ns; Loc. = LC3_A4; Fanout = 1; COMB Node = 'Mux1~94'
        Info: 3: + IC(1.000 ns) + CELL(2.000 ns) = 5.200 ns; Loc. = LC5_A5; Fanout = 1; COMB Node = 'Mux1~95'
        Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.100 ns; Loc. = LC8_A5; Fanout = 1; COMB Node = 'Mux1~97'
        Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 9.000 ns; Loc. = LC6_A5; Fanout = 1; REG Node = 'CQ[1]$latch'
        Info: Total cell delay = 7.400 ns ( 82.22 % )
        Info: Total interconnect delay = 1.600 ns ( 17.78 % )
    Info: - Smallest clock skew is 5.200 ns
        Info: + Shortest clock path from clock "CLK2" to destination register is 7.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'
            Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC3_A5; Fanout = 9; REG Node = 'BT[2]'
            Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.900 ns; Loc. = LC4_A5; Fanout = 7; COMB Node = 'Mux5~11'
            Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 7.100 ns; Loc. = LC6_A5; Fanout = 1; REG Node = 'CQ[1]$latch'
            Info: Total cell delay = 5.300 ns ( 74.65 % )
            Info: Total interconnect delay = 1.800 ns ( 25.35 % )
        Info: - Longest clock path from clock "CLK2" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_A4; Fanout = 15; REG Node = 'BT[1]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 4.100 ns
Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock "CLK2" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "BT[0]" and destination pin or register "Y[0]$latch" for clock "CLK2" (Hold time is 4.0 ns)
    Info: + Largest clock skew is 7.900 ns
        Info: + Longest clock path from clock "CLK2" to destination register is 9.800 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'
            Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_A4; Fanout = 15; REG Node = 'BT[1]'
            Info: 3: + IC(1.100 ns) + CELL(1.900 ns) = 6.000 ns; Loc. = LC4_A5; Fanout = 7; COMB Node = 'Mux5~11'
            Info: 4: + IC(1.800 ns) + CELL(2.000 ns) = 9.800 ns; Loc. = LC6_A2; Fanout = 1; REG Node = 'Y[0]$latch'
            Info: Total cell delay = 5.500 ns ( 56.12 % )
            Info: Total interconnect delay = 4.300 ns ( 43.88 % )
        Info: - Shortest clock path from clock "CLK2" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_A4; Fanout = 14; REG Node = 'BT[0]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: - Micro clock to output delay of source is 1.100 ns
    Info: - Shortest register to register delay is 2.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A4; Fanout = 14; REG Node = 'BT[0]'
        Info: 2: + IC(1.100 ns) + CELL(1.700 ns) = 2.800 ns; Loc. = LC6_A2; Fanout = 1; REG Node = 'Y[0]$latch'
        Info: Total cell delay = 1.700 ns ( 60.71 % )
        Info: Total interconnect delay = 1.100 ns ( 39.29 % )
    Info: + Micro hold delay of destination is 0.000 ns
Info: tsu for register "CQ[1]$latch" (data pin = "FEN[1]", clock pin = "CLK2") is 12.600 ns
    Info: + Longest pin to register delay is 15.600 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_173; Fanout = 1; PIN Node = 'FEN[1]'
        Info: 2: + IC(3.800 ns) + CELL(1.900 ns) = 8.800 ns; Loc. = LC3_A4; Fanout = 1; COMB Node = 'Mux1~94'
        Info: 3: + IC(1.000 ns) + CELL(2.000 ns) = 11.800 ns; Loc. = LC5_A5; Fanout = 1; COMB Node = 'Mux1~95'
        Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 13.700 ns; Loc. = LC8_A5; Fanout = 1; COMB Node = 'Mux1~97'
        Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 15.600 ns; Loc. = LC6_A5; Fanout = 1; REG Node = 'CQ[1]$latch'
        Info: Total cell delay = 10.400 ns ( 66.67 % )
        Info: Total interconnect delay = 5.200 ns ( 33.33 % )
    Info: + Micro setup delay of destination is 4.100 ns
    Info: - Shortest clock path from clock "CLK2" to destination register is 7.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'
        Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC3_A5; Fanout = 9; REG Node = 'BT[2]'
        Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.900 ns; Loc. = LC4_A5; Fanout = 7; COMB Node = 'Mux5~11'
        Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 7.100 ns; Loc. = LC6_A5; Fanout = 1; REG Node = 'CQ[1]$latch'
        Info: Total cell delay = 5.300 ns ( 74.65 % )
        Info: Total interconnect delay = 1.800 ns ( 25.35 % )
Info: tco from clock "CLK2" to destination pin "CQ[3]" through register "CQ[3]$latch" is 21.600 ns
    Info: + Longest clock path from clock "CLK2" to source register is 9.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'
        Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_A4; Fanout = 15; REG Node = 'BT[1]'
        Info: 3: + IC(1.100 ns) + CELL(1.900 ns) = 6.000 ns; Loc. = LC4_A5; Fanout = 7; COMB Node = 'Mux5~11'
        Info: 4: + IC(1.800 ns) + CELL(2.000 ns) = 9.800 ns; Loc. = LC5_A3; Fanout = 1; REG Node = 'CQ[3]$latch'
        Info: Total cell delay = 5.500 ns ( 56.12 % )
        Info: Total interconnect delay = 4.300 ns ( 43.88 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 11.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A3; Fanout = 1; REG Node = 'CQ[3]$latch'
        Info: 2: + IC(3.200 ns) + CELL(8.600 ns) = 11.800 ns; Loc. = PIN_113; Fanout = 0; PIN Node = 'CQ[3]'
        Info: Total cell delay = 8.600 ns ( 72.88 % )
        Info: Total interconnect delay = 3.200 ns ( 27.12 % )
Info: th for register "CQ[0]$latch" (data pin = "SHI[4]", clock pin = "CLK2") is 2.300 ns
    Info: + Longest clock path from clock "CLK2" to destination register is 9.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'CLK2'
        Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_A4; Fanout = 15; REG Node = 'BT[1]'
        Info: 3: + IC(1.100 ns) + CELL(1.900 ns) = 6.000 ns; Loc. = LC4_A5; Fanout = 7; COMB Node = 'Mux5~11'
        Info: 4: + IC(1.800 ns) + CELL(2.000 ns) = 9.800 ns; Loc. = LC7_A2; Fanout = 1; REG Node = 'CQ[0]$latch'
        Info: Total cell delay = 5.500 ns ( 56.12 % )
        Info: Total interconnect delay = 4.300 ns ( 43.88 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 7.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 1; PIN Node = 'SHI[4]'
        Info: 2: + IC(1.300 ns) + CELL(1.700 ns) = 3.500 ns; Loc. = LC1_A2; Fanout = 1; COMB Node = 'Mux0~97'
        Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 5.600 ns; Loc. = LC2_A2; Fanout = 1; COMB Node = 'Mux0~98'
        Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.500 ns; Loc. = LC7_A2; Fanout = 1; REG Node = 'CQ[0]$latch'
        Info: Total cell delay = 5.800 ns ( 77.33 % )
        Info: Total interconnect delay = 1.700 ns ( 22.67 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 11 warnings
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Tue Nov 27 20:57:57 2007
    Info: Elapsed time: 00:00:02