jw.tan.qmsg

可预置数字钟

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux3~12 " "Info: Detected gated clock \"Mux3~12\" as buffer" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 13 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux3~12" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "JW3\$latch CO2 ZHUANG\[2\] 10.500 ns register " "Info: tsu for register \"JW3\$latch\" (data pin = \"CO2\", clock pin = \"ZHUANG\[2\]\") is 10.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.400 ns + Longest pin register " "Info: + Longest pin to register delay is 12.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.400 ns) 3.400 ns CO2 1 PIN PIN_15 1 " "Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_15; Fanout = 1; PIN Node = 'CO2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CO2 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.900 ns) 8.000 ns Mux0~72 2 COMB LC5_C23 1 " "Info: 2: + IC(2.700 ns) + CELL(1.900 ns) = 8.000 ns; Loc. = LC5_C23; Fanout = 1; COMB Node = 'Mux0~72'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { CO2 Mux0~72 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 10.200 ns Mux0~73 3 COMB LC6_C23 1 " "Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 10.200 ns; Loc. = LC6_C23; Fanout = 1; COMB Node = 'Mux0~73'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { Mux0~72 Mux0~73 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 12.400 ns JW3\$latch 4 REG LC8_C23 1 " "Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 12.400 ns; Loc. = LC8_C23; Fanout = 1; REG Node = 'JW3\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { Mux0~73 JW3$latch } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.300 ns ( 75.00 % ) " "Info: Total cell delay = 9.300 ns ( 75.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 25.00 % ) " "Info: Total interconnect delay = 3.100 ns ( 25.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.400 ns" { CO2 Mux0~72 Mux0~73 JW3$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.400 ns" { CO2 CO2~out Mux0~72 Mux0~73 JW3$latch } { 0.000ns 0.000ns 2.700ns 0.200ns 0.200ns } { 0.000ns 3.400ns 1.900ns 2.000ns 2.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.800 ns + " "Info: + Micro setup delay of destination is 3.800 ns" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ZHUANG\[2\] destination 5.700 ns - Shortest register " "Info: - Shortest clock path from clock \"ZHUANG\[2\]\" to destination register is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns ZHUANG\[2\] 1 CLK PIN_78 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 4; CLK Node = 'ZHUANG\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ZHUANG[2] } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.700 ns) 3.800 ns Mux3~12 2 COMB LC1_C23 3 " "Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 3.800 ns; Loc. = LC1_C23; Fanout = 3; COMB Node = 'Mux3~12'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { ZHUANG[2] Mux3~12 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 5.700 ns JW3\$latch 3 REG LC8_C23 1 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 5.700 ns; Loc. = LC8_C23; Fanout = 1; REG Node = 'JW3\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { Mux3~12 JW3$latch } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 68.42 % ) " "Info: Total cell delay = 3.900 ns ( 68.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 31.58 % ) " "Info: Total interconnect delay = 1.800 ns ( 31.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { ZHUANG[2] Mux3~12 JW3$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.700 ns" { ZHUANG[2] ZHUANG[2]~out Mux3~12 JW3$latch } { 0.000ns 0.000ns 1.600ns 0.200ns } { 0.000ns 0.500ns 1.700ns 1.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.400 ns" { CO2 Mux0~72 Mux0~73 JW3$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.400 ns" { CO2 CO2~out Mux0~72 Mux0~73 JW3$latch } { 0.000ns 0.000ns 2.700ns 0.200ns 0.200ns } { 0.000ns 3.400ns 1.900ns 2.000ns 2.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { ZHUANG[2] Mux3~12 JW3$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.700 ns" { ZHUANG[2] ZHUANG[2]~out Mux3~12 JW3$latch } { 0.000ns 0.000ns 1.600ns 0.200ns } { 0.000ns 0.500ns 1.700ns 1.700ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "ZHUANG\[1\] JW1 JW1\$latch 17.200 ns register " "Info: tco from clock \"ZHUANG\[1\]\" to destination pin \"JW1\" through register \"JW1\$latch\" is 17.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ZHUANG\[1\] source 7.900 ns + Longest register " "Info: + Longest clock path from clock \"ZHUANG\[1\]\" to source register is 7.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns ZHUANG\[1\] 1 CLK PIN_184 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 4; CLK Node = 'ZHUANG\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ZHUANG[1] } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(2.000 ns) 4.200 ns Mux3~12 2 COMB LC1_C23 3 " "Info: 2: + IC(1.700 ns) + CELL(2.000 ns) = 4.200 ns; Loc. = LC1_C23; Fanout = 3; COMB Node = 'Mux3~12'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { ZHUANG[1] Mux3~12 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.700 ns) 7.900 ns JW1\$latch 3 REG LC5_C7 1 " "Info: 3: + IC(2.000 ns) + CELL(1.700 ns) = 7.900 ns; Loc. = LC5_C7; Fanout = 1; REG Node = 'JW1\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { Mux3~12 JW1$latch } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns ( 53.16 % ) " "Info: Total cell delay = 4.200 ns ( 53.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 46.84 % ) " "Info: Total interconnect delay = 3.700 ns ( 46.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { ZHUANG[1] Mux3~12 JW1$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { ZHUANG[1] ZHUANG[1]~out Mux3~12 JW1$latch } { 0.000ns 0.000ns 1.700ns 2.000ns } { 0.000ns 0.500ns 2.000ns 1.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.300 ns + Longest register pin " "Info: + Longest register to pin delay is 9.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns JW1\$latch 1 REG LC5_C7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C7; Fanout = 1; REG Node = 'JW1\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { JW1$latch } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(8.600 ns) 9.300 ns JW1 2 PIN PIN_139 0 " "Info: 2: + IC(0.700 ns) + CELL(8.600 ns) = 9.300 ns; Loc. = PIN_139; Fanout = 0; PIN Node = 'JW1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.300 ns" { JW1$latch JW1 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns ( 92.47 % ) " "Info: Total cell delay = 8.600 ns ( 92.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.700 ns ( 7.53 % ) " "Info: Total interconnect delay = 0.700 ns ( 7.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.300 ns" { JW1$latch JW1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.300 ns" { JW1$latch JW1 } { 0.000ns 0.700ns } { 0.000ns 8.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { ZHUANG[1] Mux3~12 JW1$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { ZHUANG[1] ZHUANG[1]~out Mux3~12 JW1$latch } { 0.000ns 0.000ns 1.700ns 2.000ns } { 0.000ns 0.500ns 2.000ns 1.700ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.300 ns" { JW1$latch JW1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.300 ns" { JW1$latch JW1 } { 0.000ns 0.700ns } { 0.000ns 8.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "JW1\$latch ZHUANG\[2\] ZHUANG\[1\] 2.000 ns register " "Info: th for register \"JW1\$latch\" (data pin = \"ZHUANG\[2\]\", clock pin = \"ZHUANG\[1\]\") is 2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ZHUANG\[1\] destination 7.900 ns + Longest register " "Info: + Longest clock path from clock \"ZHUANG\[1\]\" to destination register is 7.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns ZHUANG\[1\] 1 CLK PIN_184 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 4; CLK Node = 'ZHUANG\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ZHUANG[1] } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(2.000 ns) 4.200 ns Mux3~12 2 COMB LC1_C23 3 " "Info: 2: + IC(1.700 ns) + CELL(2.000 ns) = 4.200 ns; Loc. = LC1_C23; Fanout = 3; COMB Node = 'Mux3~12'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { ZHUANG[1] Mux3~12 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.700 ns) 7.900 ns JW1\$latch 3 REG LC5_C7 1 " "Info: 3: + IC(2.000 ns) + CELL(1.700 ns) = 7.900 ns; Loc. = LC5_C7; Fanout = 1; REG Node = 'JW1\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { Mux3~12 JW1$latch } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns ( 53.16 % ) " "Info: Total cell delay = 4.200 ns ( 53.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 46.84 % ) " "Info: Total interconnect delay = 3.700 ns ( 46.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { ZHUANG[1] Mux3~12 JW1$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { ZHUANG[1] ZHUANG[1]~out Mux3~12 JW1$latch } { 0.000ns 0.000ns 1.700ns 2.000ns } { 0.000ns 0.500ns 2.000ns 1.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns ZHUANG\[2\] 1 CLK PIN_78 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 4; CLK Node = 'ZHUANG\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ZHUANG[2] } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.700 ns) 3.700 ns Mux2~67 2 COMB LC1_C7 1 " "Info: 2: + IC(1.500 ns) + CELL(1.700 ns) = 3.700 ns; Loc. = LC1_C7; Fanout = 1; COMB Node = 'Mux2~67'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { ZHUANG[2] Mux2~67 } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 5.900 ns JW1\$latch 3 REG LC5_C7 1 " "Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 5.900 ns; Loc. = LC5_C7; Fanout = 1; REG Node = 'JW1\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { Mux2~67 JW1$latch } "NODE_NAME" } } { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns ( 71.19 % ) " "Info: Total cell delay = 4.200 ns ( 71.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 28.81 % ) " "Info: Total interconnect delay = 1.700 ns ( 28.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { ZHUANG[2] Mux2~67 JW1$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { ZHUANG[2] ZHUANG[2]~out Mux2~67 JW1$latch } { 0.000ns 0.000ns 1.500ns 0.200ns } { 0.000ns 0.500ns 1.700ns 2.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { ZHUANG[1] Mux3~12 JW1$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { ZHUANG[1] ZHUANG[1]~out Mux3~12 JW1$latch } { 0.000ns 0.000ns 1.700ns 2.000ns } { 0.000ns 0.500ns 2.000ns 1.700ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { ZHUANG[2] Mux2~67 JW1$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { ZHUANG[2] ZHUANG[2]~out Mux2~67 JW1$latch } { 0.000ns 0.000ns 1.500ns 0.200ns } { 0.000ns 0.500ns 1.700ns 2.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 6 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 27 14:39:36 2007 " "Info: Processing ended: Tue Nov 27 14:39:36 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}