shizhi.tan.rpt

可预置数字钟

; N/A   ; None         ; 2.900 ns   ; ZHUANG[1] ; SZI~3 ; DIAO     ;
+-------+--------------+------------+-----------+-------+----------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+-------+-------+------------+
; Slack ; Required tco ; Actual tco ; From  ; To    ; From Clock ;
+-------+--------------+------------+-------+-------+------------+
; N/A   ; None         ; 14.700 ns  ; SZI~3 ; SZ[5] ; DIAO       ;
; N/A   ; None         ; 14.100 ns  ; SZI~2 ; SZ[4] ; DIAO       ;
; N/A   ; None         ; 14.000 ns  ; SZI   ; SZ[1] ; DIAO       ;
+-------+--------------+------------+-------+-------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+-----------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To    ; To Clock ;
+---------------+-------------+-----------+-----------+-------+----------+
; N/A           ; None        ; -1.300 ns ; ZHUANG[1] ; SZI   ; DIAO     ;
; N/A           ; None        ; -1.300 ns ; ZHUANG[1] ; SZI~2 ; DIAO     ;
; N/A           ; None        ; -1.300 ns ; ZHUANG[1] ; SZI~3 ; DIAO     ;
; N/A           ; None        ; -1.500 ns ; ZHUANG[0] ; SZI   ; DIAO     ;
; N/A           ; None        ; -1.500 ns ; ZHUANG[0] ; SZI~2 ; DIAO     ;
; N/A           ; None        ; -1.500 ns ; ZHUANG[0] ; SZI~3 ; DIAO     ;
; N/A           ; None        ; -1.600 ns ; ZHUANG[2] ; SZI   ; DIAO     ;
; N/A           ; None        ; -1.600 ns ; ZHUANG[2] ; SZI~2 ; DIAO     ;
; N/A           ; None        ; -1.600 ns ; ZHUANG[2] ; SZI~3 ; DIAO     ;
+---------------+-------------+-----------+-----------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Tue Nov 27 19:56:32 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SHIZHI -c SHIZHI
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "DIAO" is an undefined clock
Info: Clock "DIAO" Internal fmax is restricted to 200.0 MHz between source register "SZI" and destination register "SZI"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.200 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C51; Fanout = 4; REG Node = 'SZI'
            Info: 2: + IC(0.200 ns) + CELL(1.000 ns) = 1.200 ns; Loc. = LC4_C51; Fanout = 4; REG Node = 'SZI'
            Info: Total cell delay = 1.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.200 ns ( 16.67 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "DIAO" to destination register is 1.900 ns
                Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'DIAO'
                Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_C51; Fanout = 4; REG Node = 'SZI'
                Info: Total cell delay = 0.500 ns ( 26.32 % )
                Info: Total interconnect delay = 1.400 ns ( 73.68 % )
            Info: - Longest clock path from clock "DIAO" to source register is 1.900 ns
                Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'DIAO'
                Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_C51; Fanout = 4; REG Node = 'SZI'
                Info: Total cell delay = 0.500 ns ( 26.32 % )
                Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: + Micro clock to output delay of source is 1.100 ns
        Info: + Micro setup delay of destination is 0.700 ns
Info: tsu for register "SZI" (data pin = "ZHUANG[2]", clock pin = "DIAO") is 3.200 ns
    Info: + Longest pin to register delay is 4.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 1; PIN Node = 'ZHUANG[2]'
        Info: 2: + IC(1.400 ns) + CELL(2.000 ns) = 3.900 ns; Loc. = LC2_C51; Fanout = 3; COMB Node = 'Equal0~24'
        Info: 3: + IC(0.200 ns) + CELL(0.300 ns) = 4.400 ns; Loc. = LC4_C51; Fanout = 4; REG Node = 'SZI'
        Info: Total cell delay = 2.800 ns ( 63.64 % )
        Info: Total interconnect delay = 1.600 ns ( 36.36 % )
    Info: + Micro setup delay of destination is 0.700 ns
    Info: - Shortest clock path from clock "DIAO" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'DIAO'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_C51; Fanout = 4; REG Node = 'SZI'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: tco from clock "DIAO" to destination pin "SZ[5]" through register "SZI~3" is 14.700 ns
    Info: + Longest clock path from clock "DIAO" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'DIAO'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_C51; Fanout = 1; REG Node = 'SZI~3'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 11.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C51; Fanout = 1; REG Node = 'SZI~3'
        Info: 2: + IC(3.100 ns) + CELL(8.600 ns) = 11.700 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'SZ[5]'
        Info: Total cell delay = 8.600 ns ( 73.50 % )
        Info: Total interconnect delay = 3.100 ns ( 26.50 % )
Info: th for register "SZI" (data pin = "ZHUANG[1]", clock pin = "DIAO") is -1.300 ns
    Info: + Longest clock path from clock "DIAO" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 3; CLK Node = 'DIAO'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_C51; Fanout = 4; REG Node = 'SZI'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro hold delay of destination is 0.900 ns
    Info: - Shortest pin to register delay is 4.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_80; Fanout = 1; PIN Node = 'ZHUANG[1]'
        Info: 2: + IC(1.400 ns) + CELL(1.700 ns) = 3.600 ns; Loc. = LC2_C51; Fanout = 3; COMB Node = 'Equal0~24'
        Info: 3: + IC(0.200 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC4_C51; Fanout = 4; REG Node = 'SZI'
        Info: Total cell delay = 2.500 ns ( 60.98 % )
        Info: Total interconnect delay = 1.600 ns ( 39.02 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Tue Nov 27 19:56:34 2007
    Info: Elapsed time: 00:00:02