counter.vhd

来自「俩个比较好的计数器的vhdl代码：一个是n位通用计数器」· VHDL 代码 · 共 38 行

package type_of_counter is
	constant size: integer:= 16;
	subtype int16 is integer range 0 to size-1;
end type_of_counter;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.type_of_counter.all;

entity counter is
port(rst: in std_logic;
	clk: in std_logic;
	counterin: in int16;
	up: in std_logic;
	load: in std_logic;
	counter_q: buffer int16);
end counter;

architecture alg of counter is
begin
	process
	begin
		wait  until clk'event and clk='1';
		if rst= '1' then
			counter_q<= 0;
		elsif load= '1' then
			counter_q<= counterin;
		else
			if up= '1' then
				counter_q<= (counter_q+1) ;
			else
				counter_q<= (counter_q-1) ;
			end if;
		end if;
	end process ;
end alg;