decoder.map.rpt

可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.

 |-- switch:inst7


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                               ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node                  ; Logic Cells ; Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                           ;
+---------------------------------------------+-------------+-----------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------+
; |decoder                                    ; 72 (1)      ; 19        ; 0           ; 12   ; 0            ; 53 (1)       ; 1 (0)             ; 18 (0)           ; 32 (0)          ; |decoder                                                                      ;
;    |fenpin:inst|                            ; 70 (62)     ; 19        ; 0           ; 0    ; 0            ; 51 (51)      ; 1 (1)             ; 18 (10)          ; 32 (24)         ; |decoder|fenpin:inst                                                          ;
;       |lpm_counter:count_rtl_0|             ; 8 (0)       ; 8         ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (0)            ; 8 (0)           ; |decoder|fenpin:inst|lpm_counter:count_rtl_0                                  ;
;          |alt_counter_stratix:wysi_counter| ; 8 (8)       ; 8         ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; |decoder|fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter ;
;    |switch:inst7|                           ; 1 (1)       ; 0         ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |decoder|switch:inst7                                                         ;
+---------------------------------------------+-------------+-----------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------+


+---------------------------------+
; Analysis & Synthesis Equations  ;
+---------------------------------+
The equations can be found in F:/MovementControl/FPGA/new/decoder.map.eqn.


+-------------------------------------------------------------------+
; Analysis & Synthesis Files Read                                   ;
+--------------------------------------------------------------------
; File Name                                                  ; Read ;
+------------------------------------------------------------+------+
; decoder.bdf                                                ; Read ;
; F:/MovementControl/FPGA/new/fenpin.v                       ; Read ;
; F:/MovementControl/FPGA/new/decode.v                       ; Read ;
; F:/MovementControl/FPGA/new/switch.v                       ; Read ;
; c:/quartus/libraries/megafunctions/lpm_counter.tdf         ; Read ;
; c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf ; Read ;
+------------------------------------------------------------+------+


+----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary        ;
+-----------------------------------------------------
; Resource                      ; Usage              ;
+-------------------------------+--------------------+
; Logic cells                   ; 72                 ;
; Total combinational functions ; 71                 ;
; Total registers               ; 19                 ;
; I/O pins                      ; 12                 ;
; Maximum fan-out node          ; switch:inst7|i4~55 ;
; Maximum fan-out               ; 18                 ;
; Total fan-out                 ; 275                ;
; Average fan-out               ; 3.27               ;
+-------------------------------+--------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+-----------------------------------------------------------------
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 32    ;
; Number of synthesis-generated cells                    ; 40    ;
; Number of WYSIWYG LUTs                                 ; 32    ;
; Number of synthesis-generated LUTs                     ; 39    ;
; Number of WYSIWYG registers                            ; 16    ;
; Number of synthesis-generated registers                ; 3     ;
; Number of cells with combinational logic only          ; 53    ;
; Number of cells with registers only                    ; 1     ;
; Number of cells with combinational logic and registers ; 18    ;
+--------------------------------------------------------+-------+


+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 8     ;
; Number of registers using SLOAD      ; 8     ;
; Number of registers using ACLR       ; 10    ;
; Number of registers using ALOAD      ; 8     ;
; Number of registers using CLK_ENABLE ; 10    ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
    Info: Processing started: Fri May 12 21:53:48 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off decoder -c decoder
Info: Found 1 design units and 1 entities in source file decoder.bdf
    Info: Found entity 1: decoder
Warning: Can't analyze file -- file F:/MovementControl/FPGA/new/decoder.v is missing
Warning: Can't analyze file -- file F:/MovementControl/FPGA/new/choose.v is missing
Warning: Can't analyze file -- file F:/MovementControl/FPGA/new/def.v is missing
Warning: Can't analyze file -- file F:/MovementControl/FPGA/new/test.v is missing
Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin clk
Warning: Can't find a definition for parameter CLR_C -- assuming 8'b00000000 was intended to be a quoted string
Warning: Can't find a definition for parameter INC_C -- assuming 8'b00000001 was intended to be a quoted string
Info: Using design file fenpin.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: fenpin
Info: Using design file decode.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: decode
Info: Using design file switch.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: switch
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: fenpin:inst|count[0]~0
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf
    Info: Found entity 1: alt_counter_stratix
Info: Implemented 84 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 1 output pins
    Info: Implemented 72 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Processing ended: Fri May 12 21:53:51 2006
    Info: Elapsed time: 00:00:03