switch.v

来自「可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.」· Verilog 代码 · 共 29 行

/*
--------------------------------------------------------------------
File Name : switch.v
Programmer(s) : woailiushui [e-mail]
Commany : IOEMCT OF TJU
Created : 2006/05/09
Description :  The program for frequency divide,change the CLK input
Modified History :
	Modified :
	Programmer :
	Description :
--------------------------------------------------------------------
*/

module switch
(
	clk1, fraction, clk, clkout
);

	input clk1;
	input fraction;
	input clk;
	output clkout;

    assign clkout = (fraction)?clk1:clk;

endmodule