decoder.csf.qmsg

可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.

{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "fenpin:inst\|count\[0\]~0 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: fenpin:inst\|count\[0\]~0" {  } { { "F:/MovementControl/FPGA/new/fenpin.v" "" "count\[0\]~0" { Text "F:/MovementControl/FPGA/new/fenpin.v" 41 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "c:/quartus/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "c:/quartus/libraries/megafunctions/lpm_counter.tdf" 221 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_stratix " "Info: Found entity 1: alt_counter_stratix" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "alt_counter_stratix" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 282 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "84 " "Info: Implemented 84 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "72 " "Info: Implemented 72 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 12 21:53:51 2006 " "Info: Processing ended: Fri May 12 21:53:51 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 12 21:53:52 2006 " "Info: Processing started: Fri May 12 21:53:52 2006" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off decoder -c decoder " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off decoder -c decoder" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "decoder EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design decoder" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "12 12 " "Info: No exact pin location assignment(s) for 12 pins of 12 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out " "Info: Pin out not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 224 1888 2064 240 "out" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "out" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { out } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { out } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "vel\[0\] " "Info: Pin vel\[0\] not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "vel\[0\]" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { vel[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "vel\[1\] " "Info: Pin vel\[1\] not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "vel\[1\]" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[1] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { vel[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "vel\[7\] " "Info: Pin vel\[7\] not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "vel\[7\]" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[7] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { vel[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "vel\[3\] " "Info: Pin vel\[3\] not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "vel\[3\]" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[3] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { vel[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "vel\[5\] " "Info: Pin vel\[5\] not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "vel\[5\]" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[5] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { vel[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "vel\[4\] " "Info: Pin vel\[4\] not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "vel\[4\]" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[4] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { vel[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "vel\[6\] " "Info: Pin vel\[6\] not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "vel\[6\]" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[6] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { vel[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "vel\[8\] " "Info: Pin vel\[8\] not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "vel\[8\]" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[8] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { vel[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "vel\[2\] " "Info: Pin vel\[2\] not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "vel\[2\]" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[2] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { vel[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 168 928 1096 184 "clk" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { clk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "reset " "Info: Pin reset not assigned to an exact location on the device" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 224 928 1096 240 "reset" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { reset } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.fld" "" "" { Floorplan "F:/MovementControl/FPGA/new/decoder.fld" "" "" { reset } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_PERIOD_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on non-logic cell registers with location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}