decoder.tan.qmsg

可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "vel\[0\] out fenpin:inst\|clk_t 12.698 ns register " "Info: Minimum tco from clock vel\[0\] to destination pin out through register fenpin:inst\|clk_t is 12.698 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vel\[0\] source 7.891 ns + Shortest register " "Info: + Shortest clock path from clock vel\[0\] to source register is 7.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns vel\[0\] 1 CLK Pin_55 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_55; Fanout = 9; CLK Node = 'vel\[0\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.815 ns) 3.290 ns switch:inst7\|i4~55 2 COMB LOOP LC_X15_Y6_N2 18 " "Info: 2: + IC(0.000 ns) + CELL(1.815 ns) = 3.290 ns; Loc. = LC_X15_Y6_N2; Fanout = 18; COMB LOOP Node = 'switch:inst7\|i4~55'" { { "Info" "ITDB_PART_OF_SCC" "fenpin:inst\|xor_clk~reg0 LC_X15_Y6_N3 " "Info: Loc. = LC_X15_Y6_N3; Node fenpin:inst\|xor_clk~reg0" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 118 -1 0 } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.815 ns" { vel[0] switch:inst7|i4~55 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.890 ns) + CELL(0.711 ns) 7.891 ns fenpin:inst\|clk_t 3 REG LC_X16_Y3_N6 2 " "Info: 3: + IC(3.890 ns) + CELL(0.711 ns) = 7.891 ns; Loc. = LC_X16_Y3_N6; Fanout = 2; REG Node = 'fenpin:inst\|clk_t'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "4.601 ns" { switch:inst7|i4~55 fenpin:inst|clk_t } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 88 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.001 ns 50.70 % " "Info: Total cell delay = 4.001 ns ( 50.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.890 ns 49.30 % " "Info: Total interconnect delay = 3.890 ns ( 49.30 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.891 ns" { vel[0] switch:inst7|i4~55 fenpin:inst|clk_t } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 88 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.583 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpin:inst\|clk_t 1 REG LC_X16_Y3_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y3_N6; Fanout = 2; REG Node = 'fenpin:inst\|clk_t'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|clk_t } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 88 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.544 ns) + CELL(0.590 ns) 1.134 ns fenpin:inst\|i14~42 2 COMB LC_X16_Y3_N1 1 " "Info: 2: + IC(0.544 ns) + CELL(0.590 ns) = 1.134 ns; Loc. = LC_X16_Y3_N1; Fanout = 1; COMB Node = 'fenpin:inst\|i14~42'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt"