decoder.tan.qmsg

可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.

{ "Info" "ITDB_FULL_TCO_RESULT" "clk out fenpin:inst\|clk_1 14.296 ns register " "Info: tco from clock clk to destination pin out through register fenpin:inst\|clk_1 is 14.296 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.217 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 8.217 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK Pin_125 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_125; Fanout = 2; CLK Node = 'clk'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 168 928 1096 184 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.105 ns) 3.580 ns switch:inst7\|i4~55 2 COMB LOOP LC_X15_Y6_N2 18 " "Info: 2: + IC(0.000 ns) + CELL(2.105 ns) = 3.580 ns; Loc. = LC_X15_Y6_N2; Fanout = 18; COMB LOOP Node = 'switch:inst7\|i4~55'" { { "Info" "ITDB_PART_OF_SCC" "fenpin:inst\|xor_clk~reg0 LC_X15_Y6_N3 " "Info: Loc. = LC_X15_Y6_N3; Node fenpin:inst\|xor_clk~reg0" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 118 -1 0 } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "2.105 ns" { clk switch:inst7|i4~55 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.926 ns) + CELL(0.711 ns) 8.217 ns fenpin:inst\|clk_1 3 REG LC_X15_Y6_N6 3 " "Info: 3: + IC(3.926 ns) + CELL(0.711 ns) = 8.217 ns; Loc. = LC_X15_Y6_N6; Fanout = 3; REG Node = 'fenpin:inst\|clk_1'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "4.637 ns" { switch:inst7|i4~55 fenpin:inst|clk_1 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.291 ns 52.22 % " "Info: Total cell delay = 4.291 ns ( 52.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.926 ns 47.78 % " "Info: Total interconnect delay = 3.926 ns ( 47.78 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "8.217 ns" { clk switch:inst7|i4~55 fenpin:inst|clk_1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 41 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.855 ns + Longest register pin " "Info: + Longest register to pin delay is 5.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpin:inst\|clk_1 1 REG LC_X15_Y6_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y6_N6; Fanout = 3; REG Node = 'fenpin:inst\|clk_1'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|clk_1 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.964 ns) + CELL(0.442 ns) 2.406 ns fenpin:inst\|i14~42 2 COMB LC_X16_Y3_N1 1 " "Info: 2: + IC(1.964 ns) + CELL(0.442 ns) = 2.406 ns; Loc. = LC_X16_Y3_N1; Fanout = 1; COMB Node = 'fenpin:inst\|i14~42'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "2.406 ns" { fenpin:inst|clk_1 fenpin:inst|i14~42 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.341 ns) + CELL(2.108 ns) 5.855 ns out 3 PIN Pin_56 0 " "Info: 3: + IC(1.341 ns) + CELL(2.108 ns) = 5.855 ns; Loc. = Pin_56; Fanout = 0; PIN Node = 'out'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "3.449 ns" { fenpin:inst|i14~42 out } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 224 1888 2064 240 "out" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.550 ns 43.55 % " "Info: Total cell delay = 2.550 ns ( 43.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.305 ns 56.45 % " "Info: Total interconnect delay = 3.305 ns ( 56.45 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "5.855 ns" { fenpin:inst|clk_1 fenpin:inst|i14~42 out } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "8.217 ns" { clk switch:inst7|i4~55 fenpin:inst|clk_1 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "5.855 ns" { fenpin:inst|clk_1 fenpin:inst|i14~42 out } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "vel\[0\] out 10.359 ns Longest " "Info: Longest tpd from source pin vel\[0\] to destination pin out is 10.359 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns vel\[0\] 1 CLK Pin_55 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_55; Fanout = 9; CLK Node = 'vel\[0\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.143 ns) + CELL(0.292 ns) 6.910 ns fenpin:inst\|i14~42 2 COMB LC_X16_Y3_N1 1 " "Info: 2: + IC(5.143 ns) + CELL(0.292 ns) = 6.910 ns; Loc. = LC_X16_Y3_N1; Fanout = 1; COMB Node = 'fenpin:inst\|i14~42'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "5.435 ns" { vel[0] fenpin:inst|i14~42 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.341 ns) + CELL(2.108 ns) 10.359 ns out 3 PIN Pin_56 0 " "Info: 3: + IC(1.341 ns) + CELL(2.108 ns) = 10.359 ns; Loc. = Pin_56; Fanout = 0; PIN Node = 'out'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "3.449 ns" { fenpin:inst|i14~42 out } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 224 1888 2064 240 "out" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.875 ns 37.41 % " "Info: Total cell delay = 3.875 ns ( 37.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.484 ns 62.59 % " "Info: Total interconnect delay = 6.484 ns ( 62.59 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "10.359 ns" { vel[0] fenpin:inst|i14~42 out } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "fenpin:inst\|clk_t vel\[1\] clk 0.717 ns register " "Info: th for register fenpin:inst\|clk_t (data pin = vel\[1\], clock pin = clk) is 0.717 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.181 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 8.181 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK Pin_125 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_125; Fanout = 2; CLK Node = 'clk'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 168 928 1096 184 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.105 ns) 3.580 ns switch:inst7\|i4~55 2 COMB LOOP LC_X15_Y6_N2 18 " "Info: 2: + IC(0.000 ns) + CELL(2.105 ns) = 3.580 ns; Loc. = LC_X15_Y6_N2; Fanout = 18; COMB LOOP Node = 'switch:inst7\|i4~55'" { { "Info" "ITDB_PART_OF_SCC" "fenpin:inst\|xor_clk~reg0 LC_X15_Y6_N3 " "Info: Loc. = LC_X15_Y6_N3; Node fenpin:inst\|xor_clk~reg0" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 118 -1 0 } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "2.105 ns" { clk switch:inst7|i4~55 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.890 ns) + CELL(0.711 ns) 8.181 ns fenpin:inst\|clk_t 3 REG LC_X16_Y3_N6 2 " "Info: 3: + IC(3.890 ns) + CELL(0.711 ns) = 8.181 ns; Loc. = LC_X16_Y3_N6; Fanout = 2; REG Node = 'fenpin:inst\|clk_t'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "4.601 ns" { switch:inst7|i4~55 fenpin:inst|clk_t } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 88 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.291 ns 52.45 % " "Info: Total cell delay = 4.291 ns ( 52.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.890 ns 47.55 % " "Info: Total interconnect delay = 3.890 ns ( 47.55 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "8.181 ns" { clk switch:inst7|i4~55 fenpin:inst|clk_t } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 88 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.479 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.479 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns vel\[1\] 1 PIN Pin_57 15 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_57; Fanout = 15; PIN Node = 'vel\[1\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[1] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.137 ns) + CELL(0.867 ns) 7.479 ns fenpin:inst\|clk_t 2 REG LC_X16_Y3_N6 2 " "Info: 2: + IC(5.137 ns) + CELL(0.867 ns) = 7.479 ns; Loc. = LC_X16_Y3_N6; Fanout = 2; REG Node = 'fenpin:inst\|clk_t'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "6.004 ns" { vel[1] fenpin:inst|clk_t } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 88 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns 31.31 % " "Info: Total cell delay = 2.342 ns ( 31.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.137 ns 68.69 % " "Info: Total interconnect delay = 5.137 ns ( 68.69 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.479 ns" { vel[1] fenpin:inst|clk_t } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "8.181 ns" { clk switch:inst7|i4~55 fenpin:inst|clk_t } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.479 ns" { vel[1] fenpin:inst|clk_t } "NODE_NAME" } } }  } 0}