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📄 decoder.tan.qmsg

📁 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] register fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] 172.53 MHz 5.796 ns Internal " "Info: Clock clk has Internal fmax of 172.53 MHz between source register fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] and destination register fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] (period= 5.796 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.535 ns + Longest register register " "Info: + Longest register to register delay is 5.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] 1 REG LC_X16_Y6_N1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y6_N1; Fanout = 7; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.294 ns) + CELL(0.292 ns) 1.586 ns fenpin:inst\|i~360 2 COMB LC_X16_Y5_N9 1 " "Info: 2: + IC(1.294 ns) + CELL(0.292 ns) = 1.586 ns; Loc. = LC_X16_Y5_N9; Fanout = 1; COMB Node = 'fenpin:inst\|i~360'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.586 ns" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] fenpin:inst|i~360 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.590 ns) 2.604 ns fenpin:inst\|i~361 3 COMB LC_X16_Y5_N6 3 " "Info: 3: + IC(0.428 ns) + CELL(0.590 ns) = 2.604 ns; Loc. = LC_X16_Y5_N6; Fanout = 3; COMB Node = 'fenpin:inst\|i~361'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.018 ns" { fenpin:inst|i~360 fenpin:inst|i~361 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.244 ns) + CELL(0.114 ns) 3.962 ns fenpin:inst\|i105~111 4 COMB LC_X16_Y6_N8 8 " "Info: 4: + IC(1.244 ns) + CELL(0.114 ns) = 3.962 ns; Loc. = LC_X16_Y6_N8; Fanout = 8; COMB Node = 'fenpin:inst\|i105~111'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.358 ns" { fenpin:inst|i~361 fenpin:inst|i105~111 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(1.112 ns) 5.535 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] 5 REG LC_X16_Y6_N0 7 " "Info: 5: + IC(0.461 ns) + CELL(1.112 ns) = 5.535 ns; Loc. = LC_X16_Y6_N0; Fanout = 7; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.573 ns" { fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 38.08 % " "Info: Total cell delay = 2.108 ns ( 38.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.427 ns 61.92 % " "Info: Total interconnect delay = 3.427 ns ( 61.92 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "5.535 ns" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] fenpin:inst|i~360 fenpin:inst|i~361 fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.217 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 8.217 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK Pin_125 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_125; Fanout = 2; CLK Node = 'clk'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 168 928 1096 184 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.105 ns) 3.580 ns switch:inst7\|i4~55 2 COMB LOOP LC_X15_Y6_N2 18 " "Info: 2: + IC(0.000 ns) + CELL(2.105 ns) = 3.580 ns; Loc. = LC_X15_Y6_N2; Fanout = 18; COMB LOOP Node = 'switch:inst7\|i4~55'" { { "Info" "ITDB_PART_OF_SCC" "fenpin:inst\|xor_clk~reg0 LC_X15_Y6_N3 " "Info: Loc. = LC_X15_Y6_N3; Node fenpin:inst\|xor_clk~reg0" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 118 -1 0 } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "2.105 ns" { clk switch:inst7|i4~55 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.926 ns) + CELL(0.711 ns) 8.217 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] 3 REG LC_X16_Y6_N0 7 " "Info: 3: + IC(3.926 ns) + CELL(0.711 ns) = 8.217 ns; Loc. = LC_X16_Y6_N0; Fanout = 7; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "4.637 ns" { switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.291 ns 52.22 % " "Info: Total cell delay = 4.291 ns ( 52.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.926 ns 47.78 % " "Info: Total interconnect delay = 3.926 ns ( 47.78 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "8.217 ns" { clk switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.217 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 8.217 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK Pin_125 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_125; Fanout = 2; CLK Node = 'clk'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 168 928 1096 184 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.105 ns) 3.580 ns switch:inst7\|i4~55 2 COMB LOOP LC_X15_Y6_N2 18 " "Info: 2: + IC(0.000 ns) + CELL(2.105 ns) = 3.580 ns; Loc. = LC_X15_Y6_N2; Fanout = 18; COMB LOOP Node = 'switch:inst7\|i4~55'" { { "Info" "ITDB_PART_OF_SCC" "fenpin:inst\|xor_clk~reg0 LC_X15_Y6_N3 " "Info: Loc. = LC_X15_Y6_N3; Node fenpin:inst\|xor_clk~reg0" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 118 -1 0 } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "2.105 ns" { clk switch:inst7|i4~55 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.926 ns) + CELL(0.711 ns) 8.217 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] 3 REG LC_X16_Y6_N1 7 " "Info: 3: + IC(3.926 ns) + CELL(0.711 ns) = 8.217 ns; Loc. = LC_X16_Y6_N1; Fanout = 7; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "4.637 ns" { switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.291 ns 52.22 % " "Info: Total cell delay = 4.291 ns ( 52.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.926 ns 47.78 % " "Info: Total interconnect delay = 3.926 ns ( 47.78 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "8.217 ns" { clk switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "8.217 ns" { clk switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "8.217 ns" { clk switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "5.535 ns" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] fenpin:inst|i~360 fenpin:inst|i~361 fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "8.217 ns" { clk switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "8.217 ns" { clk switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "vel\[0\] register fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] register fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] 172.53 MHz 5.796 ns Internal " "Info: Clock vel\[0\] has Internal fmax of 172.53 MHz between source register fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] and destination register fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] (period= 5.796 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.535 ns + Longest register register " "Info: + Longest register to register delay is 5.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] 1 REG LC_X16_Y6_N1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y6_N1; Fanout = 7; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.294 ns) + CELL(0.292 ns) 1.586 ns fenpin:inst\|i~360 2 COMB LC_X16_Y5_N9 1 " "Info: 2: + IC(1.294 ns) + CELL(0.292 ns) = 1.586 ns; Loc. = LC_X16_Y5_N9; Fanout = 1; COMB Node = 'fenpin:inst\|i~360'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.586 ns" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] fenpin:inst|i~360 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.590 ns) 2.604 ns fenpin:inst\|i~361 3 COMB LC_X16_Y5_N6 3 " "Info: 3: + IC(0.428 ns) + CELL(0.590 ns) = 2.604 ns; Loc. = LC_X16_Y5_N6; Fanout = 3; COMB Node = 'fenpin:inst\|i~361'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.018 ns" { fenpin:inst|i~360 fenpin:inst|i~361 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.244 ns) + CELL(0.114 ns) 3.962 ns fenpin:inst\|i105~111 4 COMB LC_X16_Y6_N8 8 " "Info: 4: + IC(1.244 ns) + CELL(0.114 ns) = 3.962 ns; Loc. = LC_X16_Y6_N8; Fanout = 8; COMB Node = 'fenpin:inst\|i105~111'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.358 ns" { fenpin:inst|i~361 fenpin:inst|i105~111 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(1.112 ns) 5.535 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] 5 REG LC_X16_Y6_N0 7 " "Info: 5: + IC(0.461 ns) + CELL(1.112 ns) = 5.535 ns; Loc. = LC_X16_Y6_N0; Fanout = 7; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.573 ns" { fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 38.08 % " "Info: Total cell delay = 2.108 ns ( 38.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.427 ns 61.92 % " "Info: Total interconnect delay = 3.427 ns ( 61.92 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "5.535 ns" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] fenpin:inst|i~360 fenpin:inst|i~361 fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vel\[0\] destination 7.927 ns + Shortest register " "Info: + Shortest clock path from clock vel\[0\] to destination register is 7.927 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns vel\[0\] 1 CLK Pin_55 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_55; Fanout = 9; CLK Node = 'vel\[0\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.815 ns) 3.290 ns switch:inst7\|i4~55 2 COMB LOOP LC_X15_Y6_N2 18 " "Info: 2: + IC(0.000 ns) + CELL(1.815 ns) = 3.290 ns; Loc. = LC_X15_Y6_N2; Fanout = 18; COMB LOOP Node = 'switch:inst7\|i4~55'" { { "Info" "ITDB_PART_OF_SCC" "fenpin:inst\|xor_clk~reg0 LC_X15_Y6_N3 " "Info: Loc. = LC_X15_Y6_N3; Node fenpin:inst\|xor_clk~reg0" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 118 -1 0 } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.815 ns" { vel[0] switch:inst7|i4~55 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.926 ns) + CELL(0.711 ns) 7.927 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] 3 REG LC_X16_Y6_N0 7 " "Info: 3: + IC(3.926 ns) + CELL(0.711 ns) = 7.927 ns; Loc. = LC_X16_Y6_N0; Fanout = 7; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "4.637 ns" { switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.001 ns 50.47 % " "Info: Total cell delay = 4.001 ns ( 50.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.926 ns 49.53 % " "Info: Total interconnect delay = 3.926 ns ( 49.53 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.927 ns" { vel[0] switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vel\[0\] source 7.927 ns - Longest register " "Info: - Longest clock path from clock vel\[0\] to source register is 7.927 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns vel\[0\] 1 CLK Pin_55 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_55; Fanout = 9; CLK Node = 'vel\[0\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.815 ns) 3.290 ns switch:inst7\|i4~55 2 COMB LOOP LC_X15_Y6_N2 18 " "Info: 2: + IC(0.000 ns) + CELL(1.815 ns) = 3.290 ns; Loc. = LC_X15_Y6_N2; Fanout = 18; COMB LOOP Node = 'switch:inst7\|i4~55'" { { "Info" "ITDB_PART_OF_SCC" "fenpin:inst\|xor_clk~reg0 LC_X15_Y6_N3 " "Info: Loc. = LC_X15_Y6_N3; Node fenpin:inst\|xor_clk~reg0" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 118 -1 0 } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.815 ns" { vel[0] switch:inst7|i4~55 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.926 ns) + CELL(0.711 ns) 7.927 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] 3 REG LC_X16_Y6_N1 7 " "Info: 3: + IC(3.926 ns) + CELL(0.711 ns) = 7.927 ns; Loc. = LC_X16_Y6_N1; Fanout = 7; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "4.637 ns" { switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.001 ns 50.47 % " "Info: Total cell delay = 4.001 ns ( 50.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.926 ns 49.53 % " "Info: Total interconnect delay = 3.926 ns ( 49.53 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.927 ns" { vel[0] switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.927 ns" { vel[0] switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.927 ns" { vel[0] switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "5.535 ns" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] fenpin:inst|i~360 fenpin:inst|i~361 fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.927 ns" { vel[0] switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.927 ns" { vel[0] switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[7\] vel\[3\] vel\[0\] 7.020 ns register " "Info: tsu for register fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[7\] (data pin = vel\[3\], clock pin = vel\[0\]) is 7.020 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.910 ns + Longest pin register " "Info: + Longest pin to register delay is 14.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns vel\[3\] 1 PIN Pin_61 10 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_61; Fanout = 10; PIN Node = 'vel\[3\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[3] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.326 ns) + CELL(0.564 ns) 8.365 ns fenpin:inst\|i~22COUT0 2 COMB LC_X16_Y4_N1 2 " "Info: 2: + IC(6.326 ns) + CELL(0.564 ns) = 8.365 ns; Loc. = LC_X16_Y4_N1; Fanout = 2; COMB Node = 'fenpin:inst\|i~22COUT0'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "6.890 ns" { vel[3] fenpin:inst|i~22COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 8.443 ns fenpin:inst\|i~23COUT0 3 COMB LC_X16_Y4_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 8.443 ns; Loc. = LC_X16_Y4_N2; Fanout = 2; COMB Node = 'fenpin:inst\|i~23COUT0'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "0.078 ns" { fenpin:inst|i~22COUT0 fenpin:inst|i~23COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 8.521 ns fenpin:inst\|i~24COUT0 4 COMB LC_X16_Y4_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 8.521 ns; Loc. = LC_X16_Y4_N3; Fanout = 2; COMB Node = 'fenpin:inst\|i~24COUT0'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "0.078 ns" { fenpin:inst|i~23COUT0 fenpin:inst|i~24COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 8.699 ns fenpin:inst\|i~25COUT 5 COMB LC_X16_Y4_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 8.699 ns; Loc. = LC_X16_Y4_N4; Fanout = 3; COMB Node = 'fenpin:inst\|i~25COUT'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "0.178 ns" { fenpin:inst|i~24COUT0 fenpin:inst|i~25COUT } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 9.320 ns fenpin:inst\|i~28 6 COMB LC_X16_Y4_N7 1 " "Info: 6: + IC(0.000 ns) + CELL(0.621 ns) = 9.320 ns; Loc. = LC_X16_Y4_N7; Fanout = 1; COMB Node = 'fenpin:inst\|i~28'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "0.621 ns" { fenpin:inst|i~25COUT fenpin:inst|i~28 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.442 ns) 10.961 ns fenpin:inst\|i~360 7 COMB LC_X16_Y5_N9 1 " "Info: 7: + IC(1.199 ns) + CELL(0.442 ns) = 10.961 ns; Loc. = LC_X16_Y5_N9; Fanout = 1; COMB Node = 'fenpin:inst\|i~360'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.641 ns" { fenpin:inst|i~28 fenpin:inst|i~360 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.590 ns) 11.979 ns fenpin:inst\|i~361 8 COMB LC_X16_Y5_N6 3 " "Info: 8: + IC(0.428 ns) + CELL(0.590 ns) = 11.979 ns; Loc. = LC_X16_Y5_N6; Fanout = 3; COMB Node = 'fenpin:inst\|i~361'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.018 ns" { fenpin:inst|i~360 fenpin:inst|i~361 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.244 ns) + CELL(0.114 ns) 13.337 ns fenpin:inst\|i105~111 9 COMB LC_X16_Y6_N8 8 " "Info: 9: + IC(1.244 ns) + CELL(0.114 ns) = 13.337 ns; Loc. = LC_X16_Y6_N8; Fanout = 8; COMB Node = 'fenpin:inst\|i105~111'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.358 ns" { fenpin:inst|i~361 fenpin:inst|i105~111 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(1.112 ns) 14.910 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[7\] 10 REG LC_X16_Y6_N7 5 " "Info: 10: + IC(0.461 ns) + CELL(1.112 ns) = 14.910 ns; Loc. = LC_X16_Y6_N7; Fanout = 5; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[7\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.573 ns" { fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.252 ns 35.22 % " "Info: Total cell delay = 5.252 ns ( 35.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.658 ns 64.78 % " "Info: Total interconnect delay = 9.658 ns ( 64.78 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "14.910 ns" { vel[3] fenpin:inst|i~22COUT0 fenpin:inst|i~23COUT0 fenpin:inst|i~24COUT0 fenpin:inst|i~25COUT fenpin:inst|i~28 fenpin:inst|i~360 fenpin:inst|i~361 fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vel\[0\] destination 7.927 ns - Shortest register " "Info: - Shortest clock path from clock vel\[0\] to destination register is 7.927 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns vel\[0\] 1 CLK Pin_55 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = Pin_55; Fanout = 9; CLK Node = 'vel\[0\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { vel[0] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.815 ns) 3.290 ns switch:inst7\|i4~55 2 COMB LOOP LC_X15_Y6_N2 18 " "Info: 2: + IC(0.000 ns) + CELL(1.815 ns) = 3.290 ns; Loc. = LC_X15_Y6_N2; Fanout = 18; COMB LOOP Node = 'switch:inst7\|i4~55'" { { "Info" "ITDB_PART_OF_SCC" "fenpin:inst\|xor_clk~reg0 LC_X15_Y6_N3 " "Info: Loc. = LC_X15_Y6_N3; Node fenpin:inst\|xor_clk~reg0" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|xor_clk~reg0 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 118 -1 0 } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.815 ns" { vel[0] switch:inst7|i4~55 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.926 ns) + CELL(0.711 ns) 7.927 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[7\] 3 REG LC_X16_Y6_N7 5 " "Info: 3: + IC(3.926 ns) + CELL(0.711 ns) = 7.927 ns; Loc. = LC_X16_Y6_N7; Fanout = 5; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[7\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "4.637 ns" { switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.001 ns 50.47 % " "Info: Total cell delay = 4.001 ns ( 50.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.926 ns 49.53 % " "Info: Total interconnect delay = 3.926 ns ( 49.53 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.927 ns" { vel[0] switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] } "NODE_NAME" } } }  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "14.910 ns" { vel[3] fenpin:inst|i~22COUT0 fenpin:inst|i~23COUT0 fenpin:inst|i~24COUT0 fenpin:inst|i~25COUT fenpin:inst|i~28 fenpin:inst|i~360 fenpin:inst|i~361 fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "7.927 ns" { vel[0] switch:inst7|i4~55 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] } "NODE_NAME" } } }  } 0}
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