decoder.tan.qmsg

可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.

{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "switch:inst7\|i4~55 " "Info: Node switch:inst7\|i4~55" {  } { { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "fenpin:inst\|clk_1 " "Info: Node fenpin:inst\|clk_1" {  } { { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 41 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "fenpin:inst\|xor_clk~reg0 " "Info: Node fenpin:inst\|xor_clk~reg0" {  } { { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 118 -1 0 } }  } 0}  } { { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 41 -1 0 } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 118 -1 0 } }  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 168 928 1096 184 "clk" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "vel\[0\] " "Info: Assuming node vel\[0\] is an undefined clock" {  } { { "F:/MovementControl/FPGA/new/decoder.bdf" "" "" { Schematic "F:/MovementControl/FPGA/new/decoder.bdf" { { 240 928 1096 256 "vel\[8..0\]" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "vel\[0\]" } } } }  } 0}  } {  } 0}
{ "Warning" "WTDB_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITDB_GATED_CLK" "switch:inst7\|i4~55 " "Info: Detected gated clock switch:inst7\|i4~55 as buffer" {  } { { "F:/MovementControl/FPGA/new/switch.v" "" "" { Text "F:/MovementControl/FPGA/new/switch.v" 26 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "switch:inst7\|i4~55" } } } }  } 0}  } {  } 0}