decoder.fit.qmsg

可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.

{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF " "Info: Statistics of I/O pins that use the same VCCIO and VREF" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 3.30 10 1 0 " "Info: Number of I/O pins in group: 11 (unused VREF, 3.30 VCCIO, 10 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: Details of I/O bank before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 18 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 24 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "Info: Details of I/O bank after I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 14 7 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 14 total pin(s) used --  7 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 24 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.630 ns register register " "Info: Estimated most critical path is register to register delay of 5.630 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[6\] 1 REG LAB_X16_Y6 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y6; Fanout = 7; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[6\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[6] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.590 ns) 0.961 ns fenpin:inst\|i~362 2 COMB LAB_X15_Y6 1 " "Info: 2: + IC(0.371 ns) + CELL(0.590 ns) = 0.961 ns; Loc. = LAB_X15_Y6; Fanout = 1; COMB Node = 'fenpin:inst\|i~362'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "0.961 ns" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[6] fenpin:inst|i~362 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.590 ns) 2.326 ns fenpin:inst\|i~366 3 COMB LAB_X17_Y6 2 " "Info: 3: + IC(0.775 ns) + CELL(0.590 ns) = 2.326 ns; Loc. = LAB_X17_Y6; Fanout = 2; COMB Node = 'fenpin:inst\|i~366'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.365 ns" { fenpin:inst|i~362 fenpin:inst|i~366 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.590 ns) 3.287 ns fenpin:inst\|i105~110 4 COMB LAB_X16_Y6 1 " "Info: 4: + IC(0.371 ns) + CELL(0.590 ns) = 3.287 ns; Loc. = LAB_X16_Y6; Fanout = 1; COMB Node = 'fenpin:inst\|i105~110'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "0.961 ns" { fenpin:inst|i~366 fenpin:inst|i105~110 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.590 ns) 4.017 ns fenpin:inst\|i105~111 5 COMB LAB_X16_Y6 8 " "Info: 5: + IC(0.140 ns) + CELL(0.590 ns) = 4.017 ns; Loc. = LAB_X16_Y6; Fanout = 8; COMB Node = 'fenpin:inst\|i105~111'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "0.730 ns" { fenpin:inst|i105~110 fenpin:inst|i105~111 } "NODE_NAME" } } } { "F:/MovementControl/FPGA/new/fenpin.v" "" "" { Text "F:/MovementControl/FPGA/new/fenpin.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.501 ns) + CELL(1.112 ns) 5.630 ns fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[7\] 6 REG LAB_X16_Y6 5 " "Info: 6: + IC(0.501 ns) + CELL(1.112 ns) = 5.630 ns; Loc. = LAB_X16_Y6; Fanout = 5; REG Node = 'fenpin:inst\|lpm_counter:count_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[7\]'" {  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "1.613 ns" { fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.472 ns 61.67 % " "Info: Total cell delay = 3.472 ns ( 61.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.158 ns 38.33 % " "Info: Total interconnect delay = 2.158 ns ( 38.33 % )" {  } {  } 0}  } { { "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" "" "" { Report "F:/MovementControl/FPGA/new/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "F:/MovementControl/FPGA/new/db/decoder.quartus_db" { Floorplan "" "" "5.630 ns" { fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[6] fenpin:inst|i~362 fenpin:inst|i~366 fenpin:inst|i105~110 fenpin:inst|i105~111 fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "1 " "Info: Fitter placement operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "1 " "Info: Fitter routing operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 12 21:54:02 2006 " "Info: Processing ended: Fri May 12 21:54:02 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}