decoder.map.eqn

可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.

F1_safe_q[2]_carry_eqn = F1L5;
F1_safe_q[2]_lut_out = F1_safe_q[2] $ !F1_safe_q[2]_carry_eqn;
F1_safe_q[2]_reg_input = !B1L22 & F1_safe_q[2]_lut_out;
F1_safe_q[2] = DFFEA(F1_safe_q[2]_reg_input, !D1L1, reset, , , , );

--F1L7 is fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[2]~COUT
--operation mode is arithmetic

F1L7 = CARRY(F1_safe_q[2] & !F1L5);


--F1_safe_q[1] is fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]
--operation mode is arithmetic

F1_safe_q[1]_carry_eqn = F1L3;
F1_safe_q[1]_lut_out = F1_safe_q[1] $ F1_safe_q[1]_carry_eqn;
F1_safe_q[1]_reg_input = !B1L22 & F1_safe_q[1]_lut_out;
F1_safe_q[1] = DFFEA(F1_safe_q[1]_reg_input, !D1L1, reset, , , , );

--F1L5 is fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[1]~COUT
--operation mode is arithmetic

F1L5 = CARRY(!F1L3 # !F1_safe_q[1]);


--F1_safe_q[0] is fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]
--operation mode is arithmetic

F1_safe_q[0]_lut_out = !F1_safe_q[0];
F1_safe_q[0]_reg_input = !B1L22 & F1_safe_q[0]_lut_out;
F1_safe_q[0] = DFFEA(F1_safe_q[0]_reg_input, !D1L1, reset, , , , );

--F1L3 is fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[0]~COUT
--operation mode is arithmetic

F1L3 = CARRY(F1_safe_q[0]);


--B1_clk_1 is fenpin:inst|clk_1
--operation mode is normal

B1_clk_1_lut_out = vel[0] & !B1L02 # !vel[0] & (B1L85 & B1L02 # !B1L36);
B1_clk_1 = DFFEA(B1_clk_1_lut_out, !D1L1, reset, , , , );


--B1_clk_t is fenpin:inst|clk_t
--operation mode is normal

B1_clk_t_lut_out = B1_clk_t & B1L87 # !B1L38;
B1_clk_t = DFFEA(B1_clk_t_lut_out, D1L1, reset, , vel[1], , );


--B1L91 is fenpin:inst|i14~42
--operation mode is normal

B1L91 = B1_clk_1 & (B1_clk_t # vel[0] # !vel[1]);


--B1L45 is fenpin:inst|i~352
--operation mode is normal

B1L45 = F1_safe_q[6] & (F1_safe_q[2] $ B1L82 # !B1L63) # !F1_safe_q[6] & (B1L63 # F1_safe_q[2] $ B1L82);


--B1L55 is fenpin:inst|i~353
--operation mode is normal

B1L55 = F1_safe_q[4] & (F1_safe_q[3] $ B1L03 # !B1L23) # !F1_safe_q[4] & (B1L23 # F1_safe_q[3] $ B1L03);


--B1L65 is fenpin:inst|i~354
--operation mode is normal

B1L65 = F1_safe_q[5] & (F1_safe_q[0] $ B1L42 # !B1L43) # !F1_safe_q[5] & (B1L43 # F1_safe_q[0] $ B1L42);


--B1L75 is fenpin:inst|i~355
--operation mode is normal

B1L75 = F1_safe_q[7] & (F1_safe_q[1] $ B1L62 # !B1L83) # !F1_safe_q[7] & (B1L83 # F1_safe_q[1] $ B1L62);


--B1L85 is fenpin:inst|i~356
--operation mode is normal

B1L85 = B1L45 # B1L55 # B1L65 # B1L75;


--B1L95 is fenpin:inst|i~357
--operation mode is normal

B1L95 = F1_safe_q[6] & (F1_safe_q[2] $ B1L34 # !B1L15) # !F1_safe_q[6] & (B1L15 # F1_safe_q[2] $ B1L34);


--B1L06 is fenpin:inst|i~358
--operation mode is normal

B1L06 = F1_safe_q[4] & (F1_safe_q[3] $ B1L54 # !B1L74) # !F1_safe_q[4] & (B1L74 # F1_safe_q[3] $ B1L54);


--B1L16 is fenpin:inst|i~359
--operation mode is normal

B1L16 = F1_safe_q[5] & (F1_safe_q[0] $ B1L93 # !B1L94) # !F1_safe_q[5] & (B1L94 # F1_safe_q[0] $ B1L93);


--B1L26 is fenpin:inst|i~360
--operation mode is normal

B1L26 = F1_safe_q[7] & (F1_safe_q[1] $ B1L14 # !B1L35) # !F1_safe_q[7] & (B1L35 # F1_safe_q[1] $ B1L14);


--B1L36 is fenpin:inst|i~361
--operation mode is normal

B1L36 = B1L95 # B1L06 # B1L16 # B1L26;


--B1L46 is fenpin:inst|i~362
--operation mode is normal

B1L46 = F1_safe_q[6] & (F1_safe_q[2] $ vel[3] # !vel[7]) # !F1_safe_q[6] & (vel[7] # F1_safe_q[2] $ vel[3]);


--B1L56 is fenpin:inst|i~363
--operation mode is normal

B1L56 = F1_safe_q[4] & (F1_safe_q[3] $ vel[4] # !vel[5]) # !F1_safe_q[4] & (vel[5] # F1_safe_q[3] $ vel[4]);


--B1L66 is fenpin:inst|i~364
--operation mode is normal

B1L66 = F1_safe_q[5] & (F1_safe_q[0] $ vel[1] # !vel[6]) # !F1_safe_q[5] & (vel[6] # F1_safe_q[0] $ vel[1]);


--B1L76 is fenpin:inst|i~365
--operation mode is normal

B1L76 = F1_safe_q[7] & (F1_safe_q[1] $ vel[2] # !vel[8]) # !F1_safe_q[7] & (vel[8] # F1_safe_q[1] $ vel[2]);


--B1L86 is fenpin:inst|i~366
--operation mode is normal

B1L86 = B1L46 # B1L56 # B1L66 # B1L76;


--B1L96 is fenpin:inst|i~367
--operation mode is normal

B1L96 = F1_safe_q[7] # F1_safe_q[5] $ vel[7];


--B1L07 is fenpin:inst|i~368
--operation mode is normal

B1L07 = F1_safe_q[3] & (F1_safe_q[2] $ vel[4] # !vel[5]) # !F1_safe_q[3] & (vel[5] # F1_safe_q[2] $ vel[4]);


--B1L17 is fenpin:inst|i~369
--operation mode is normal

B1L17 = F1_safe_q[4] & (F1_safe_q[1] $ vel[3] # !vel[6]) # !F1_safe_q[4] & (vel[6] # F1_safe_q[1] $ vel[3]);


--B1L27 is fenpin:inst|i~370
--operation mode is normal

B1L27 = F1_safe_q[6] & (F1_safe_q[0] $ vel[2] # !vel[8]) # !F1_safe_q[6] & (vel[8] # F1_safe_q[0] $ vel[2]);


--B1L37 is fenpin:inst|i~371
--operation mode is normal

B1L37 = B1L96 # B1L07 # B1L17 # B1L27;


--B1L02 is fenpin:inst|i97~104
--operation mode is normal

B1L02 = vel[0] & B1L37 & (!B1L86 # !B1_clk_1) # !vel[0] & B1_clk_1;


--B1L48Q is fenpin:inst|xor_clk~reg0
--operation mode is normal

B1L48Q_lut_out = !B1L48Q;
B1L48Q = DFFEA(B1L48Q_lut_out, B1_clk_1, VCC, , vel[0], , );


--D1L1 is switch:inst7|i4~55
--operation mode is normal

D1L1 = clk $ (!vel[0] # !B1L48Q);


--B1L47 is fenpin:inst|i~372
--operation mode is normal

B1L47 = B1_cnt[2] & (B1_cnt[6] $ vel[7] # !vel[3]) # !B1_cnt[2] & (vel[3] # B1_cnt[6] $ vel[7]);


--B1L57 is fenpin:inst|i~373
--operation mode is normal

B1L57 = B1_cnt[3] & (B1_cnt[4] $ vel[5] # !vel[4]) # !B1_cnt[3] & (vel[4] # B1_cnt[4] $ vel[5]);


--B1L67 is fenpin:inst|i~374
--operation mode is normal

B1L67 = B1_cnt[0] & (B1_cnt[5] $ vel[6] # !vel[1]) # !B1_cnt[0] & (vel[1] # B1_cnt[5] $ vel[6]);


--B1L77 is fenpin:inst|i~375
--operation mode is normal

B1L77 = B1_cnt[1] & (B1_cnt[7] $ vel[8] # !vel[2]) # !B1_cnt[1] & (vel[2] # B1_cnt[7] $ vel[8]);


--B1L87 is fenpin:inst|i~376
--operation mode is normal

B1L87 = B1L47 # B1L57 # B1L67 # B1L77;


--B1L97 is fenpin:inst|i~377
--operation mode is normal

B1L97 = B1_cnt[7] # B1_cnt[5] $ vel[7];


--B1L08 is fenpin:inst|i~378
--operation mode is normal

B1L08 = B1_cnt[2] & (B1_cnt[3] $ vel[5] # !vel[4]) # !B1_cnt[2] & (vel[4] # B1_cnt[3] $ vel[5]);


--B1L18 is fenpin:inst|i~379
--operation mode is normal

B1L18 = B1_cnt[1] & (B1_cnt[4] $ vel[6] # !vel[3]) # !B1_cnt[1] & (vel[3] # B1_cnt[4] $ vel[6]);


--B1L28 is fenpin:inst|i~380
--operation mode is normal

B1L28 = B1_cnt[0] & (B1_cnt[6] $ vel[8] # !vel[2]) # !B1_cnt[0] & (vel[2] # B1_cnt[6] $ vel[8]);


--B1L38 is fenpin:inst|i~381
--operation mode is normal

B1L38 = B1L97 # B1L08 # B1L18 # B1L28;


--B1L12 is fenpin:inst|i105~110
--operation mode is normal

B1L12 = B1L86 # !B1L37;


--B1L22 is fenpin:inst|i105~111
--operation mode is normal

B1L22 = vel[0] & !B1L12 # !vel[0] & !B1L85 & B1L36;


--B1L32 is fenpin:inst|i156~0
--operation mode is normal

B1L32 = B1L38 & !B1L87;


--~GND is ~GND
--operation mode is normal

~GND = GND;


--vel[0] is vel[0]
--operation mode is input

vel[0] = INPUT();


--vel[1] is vel[1]
--operation mode is input

vel[1] = INPUT();


--vel[7] is vel[7]
--operation mode is input

vel[7] = INPUT();


--vel[3] is vel[3]
--operation mode is input

vel[3] = INPUT();


--vel[5] is vel[5]
--operation mode is input

vel[5] = INPUT();


--vel[4] is vel[4]
--operation mode is input

vel[4] = INPUT();


--vel[6] is vel[6]
--operation mode is input

vel[6] = INPUT();


--vel[8] is vel[8]
--operation mode is input

vel[8] = INPUT();


--vel[2] is vel[2]
--operation mode is input

vel[2] = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--reset is reset
--operation mode is input

reset = INPUT();


--out is out
--operation mode is output

out = OUTPUT(B1L91);