📄 decoder.fit.rpt
字号:
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.20) ; Number of LABs (Total = 10) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 0 ;
; 10 ; 4 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 4.80) ; Number of LABs (Total = 10) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 1 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 11.70) ; Number of LABs (Total = 10) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 0 ;
; 20 ; 1 ;
; 21 ; 2 ;
+----------------------------------------------+------------------------------+
+------------------+
; Fitter Messages ;
+------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
Info: Processing started: Fri May 12 21:53:52 2006
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off decoder -c decoder
Info: Selected device EP1C3T144C8 for design decoder
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6T144C8 is compatible
Info: No exact pin location assignment(s) for 12 pins of 12 total pins
Info: Pin out not assigned to an exact location on the device
Info: Pin vel[0] not assigned to an exact location on the device
Info: Pin vel[1] not assigned to an exact location on the device
Info: Pin vel[7] not assigned to an exact location on the device
Info: Pin vel[3] not assigned to an exact location on the device
Info: Pin vel[5] not assigned to an exact location on the device
Info: Pin vel[4] not assigned to an exact location on the device
Info: Pin vel[6] not assigned to an exact location on the device
Info: Pin vel[8] not assigned to an exact location on the device
Info: Pin vel[2] not assigned to an exact location on the device
Info: Pin clk not assigned to an exact location on the device
Info: Pin reset not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency
Info: Performing register packing on non-logic cell registers with location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal switch:inst7|i4~55 to use Global clock
Info: Automatically promoted signal reset to use Global clock in Pin 17
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start DSP Scan-chain Inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density
Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF
Info: Number of I/O pins in group: 11 (unused VREF, 3.30 VCCIO, 10 input, 1 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: Details of I/O bank before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used -- 18 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 24 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: Details of I/O bank after I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 14 total pin(s) used -- 7 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 24 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 5.630 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y6; Fanout = 7; REG Node = 'fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[6]'
Info: 2: + IC(0.371 ns) + CELL(0.590 ns) = 0.961 ns; Loc. = LAB_X15_Y6; Fanout = 1; COMB Node = 'fenpin:inst|i~362'
Info: 3: + IC(0.775 ns) + CELL(0.590 ns) = 2.326 ns; Loc. = LAB_X17_Y6; Fanout = 2; COMB Node = 'fenpin:inst|i~366'
Info: 4: + IC(0.371 ns) + CELL(0.590 ns) = 3.287 ns; Loc. = LAB_X16_Y6; Fanout = 1; COMB Node = 'fenpin:inst|i105~110'
Info: 5: + IC(0.140 ns) + CELL(0.590 ns) = 4.017 ns; Loc. = LAB_X16_Y6; Fanout = 8; COMB Node = 'fenpin:inst|i105~111'
Info: 6: + IC(0.501 ns) + CELL(1.112 ns) = 5.630 ns; Loc. = LAB_X16_Y6; Fanout = 5; REG Node = 'fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7]'
Info: Total cell delay = 3.472 ns ( 61.67 % )
Info: Total interconnect delay = 2.158 ns ( 38.33 % )
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 1 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 1 seconds
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Fri May 12 21:54:02 2006
Info: Elapsed time: 00:00:09
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