decoder.tan.rpt

可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.

; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                             ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                      ; From                                                                           ; To                                                                             ;
+------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+
; Worst-case tsu         ; N/A   ; None          ; 7.020 ns                         ; vel[3]                                                                         ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] ;
; Worst-case tco         ; N/A   ; None          ; 14.296 ns                        ; fenpin:inst|clk_1                                                              ; out                                                                            ;
; Worst-case tpd         ; N/A   ; None          ; 10.359 ns                        ; vel[0]                                                                         ; out                                                                            ;
; Worst-case th          ; N/A   ; None          ; 0.717 ns                         ; vel[1]                                                                         ; fenpin:inst|clk_t                                                              ;
; Worst-case minimum tco ; N/A   ; None          ; 12.698 ns                        ; fenpin:inst|clk_t                                                              ; out                                                                            ;
; Worst-case minimum tpd ; N/A   ; None          ; 10.118 ns                        ; vel[1]                                                                         ; out                                                                            ;
; Clock Setup: 'vel[0]'  ; N/A   ; None          ; 172.53 MHz ( period = 5.796 ns ) ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] ;
; Clock Setup: 'clk'     ; N/A   ; None          ; 172.53 MHz ( period = 5.796 ns ) ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] ;
+------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; vel[0]          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                   ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Actual fmax (period)                           ; From                                                                           ; To                                                                             ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 172.53 MHz ( period = 5.796 ns )               ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; 172.53 MHz ( period = 5.796 ns )               ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; 172.53 MHz ( period = 5.796 ns )               ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[2] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; 172.53 MHz ( period = 5.796 ns )               ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; 172.53 MHz ( period = 5.796 ns )               ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[5] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; 172.53 MHz ( period = 5.796 ns )               ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[4] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; 172.53 MHz ( period = 5.796 ns )               ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[6] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; 172.53 MHz ( period = 5.796 ns )               ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; 172.92 MHz ( period = 5.783 ns )               ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[4] ; fenpin:inst|lpm_counter:count_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] ; clk        ; clk      ; None                        ; None                      ; None                    ;