i2c_blk_ver.v

Xilinx的I2C总线控制器

//--------------------------------------------------
//  
//      Verilog code generated by Visual HDL
//
//  Design Unit:
//  ------------
//      Unit    Name  :  i2c_blk
//      Library Name  :  i2c_work
//  
//      Creation Date :  Mon Mar 12 10:41:16 2001
//      Version       :  6.7.0 build 17 from Oct  2 2000
//  
//  Options Used:
//  -------------
//      Target
//         HDL        :  Verilog
//         Purpose    :  Synthesis
//         Vendor     :  Design Compiler
//  
//      Style
//         Use Procedures                 :  No
//         Code Destination               :  Combined file
//         Attach Directives              :  Yes
//         Structural                     :  No
//         Preserve spacing for free text :  Yes
//         Sort Ports by mode             :  No
//         Declaration alignment          :  No
//
//--------------------------------------------------
//--------------------------------------------------
//  
//  Library Name :  i2c_work
//  Unit    Name :  i2c_blk
//  Unit    Type :  Block Diagram
//  
//----------------------------------------------------
 
module i2c_blk (sda, scl, addr_bus, data_bus, as, ds, r_w, dtack, irq, mcf, clk,
                reset);
 
  parameter I2C_ADDRESS = 16'b0000000000000000;
  //   I2C bus signals
  inout sda;
  inout scl;
  //   uC interface signals
  input [23:0] addr_bus;
  inout [7:0] data_bus;
  input as;                //   address strobe, active low
  input ds;                //   data strobe, active low
  input r_w;               //   read/write
  output dtack;            //   data transfer acknowledge
  output irq;              //   interrupt request
  inout mcf;               //   temporary output for testing
  //   clock and reset
  input clk;
  input reset;
 
  //   status register
  //  signal mcf			: std_logic;		-- indicates a completed data byte transfer
  wire maas;               //   indicates the chip has been addressed as I2c slave
  //   ****************************** Signal Declarations ****************************
  //   control register
  wire [7:0] madr;         //   I2C address
  wire mal;                //   indicates that arbitration for the i2c bus is lost
  //   resets for certain status and control register bits
  wire mal_bit_reset;      //   resets arbitration lost indicator
  wire mbb;                //   indicates the i2c bus is busy
  wire mbcr_wr;            //   indicates the uC has written the MBCR
  wire [7:0] mbdr_i2c;     //   i2c data register
  //   data registers
  //   there are two data registers, one to hold the uC data when the chip is transmitting on I2C
  //   and one to hold the I2C data when the chip is receiving. This allows the two registers to
  //   be clocked by different clocks
  wire [7:0] mbdr_micro;   //   uC data register
  wire mbdr_read;          //   indicates the mbdr_i2c register has been
  wire men;                //   i2c enable - used as i2c reset
  wire mien;               //   interrupt enable
  wire mif;                //   interrupt pending
  wire mif_bit_reset;      //   resets interrupt pending bit
  wire msta;               //   i2c master/slave select
  wire msta_rst;           //   resets master/slave select when arbitration is lost
  wire mtx;                //   master read/write
  wire rsta;               //   generate a repeated start
  wire rxak;               //   value of received acknowledge
  wire srw;                //   slave read/write
  wire txak;               //   value of acknowledge to be transmitted
 
 
  //   read by the uC
  //   ****************************** Component Instantiations ****************************
  //   Instantiate the I2C Controller and connect it
  i2c_control  I2C_CTRL
    (
     .sda(sda),
     .scl(scl),
     .txak(txak),
     .msta(msta),
     .msta_rst(msta_rst),
     .rsta(rsta),
     .mtx(mtx),
     .mbdr_micro(mbdr_micro[7:0]),
     .madr(madr[7:0]),
     .mbb(mbb),
     .mcf(mcf),
     .maas(maas),
     .mal(mal),
     .srw(srw),
     .mif(mif),
     .rxak(rxak),
     .mbdr_i2c(mbdr_i2c[7:0]),
     .mbcr_wr(mbcr_wr),
     .mif_bit_reset(mif_bit_reset),
     .mal_bit_reset(mal_bit_reset),
     .sys_clk(clk),
     .reset(men));
 
  //   I2C bus signals
  //   interface signals from uP interface
  //   Instantiate the uC interface and connect it
  uC_interface #(I2C_ADDRESS)  uC_CTRL
    (
     .clk(clk),
     .reset(reset),
     .addr_bus(addr_bus[23:0]),
     .data_bus(data_bus[7:0]),
     .as(as),
     .ds(ds),
     .r_w(r_w),
     .dtack(dtack),
     .irq(irq),
     .madr(madr[7:0]),
     .men(men),
     .mien(mien),
     .msta(msta),
     .mtx(mtx),
     .txak(txak),
     .rsta(rsta),
     .mbcr_wr(mbcr_wr),
     .mcf(mcf),
     .maas(maas),
     .mbb(mbb),
     .mal(mal),
     .srw(srw),
     .mif(mif),
     .rxak(rxak),
     .mal_bit_reset(mal_bit_reset),
     .mif_bit_reset(mif_bit_reset),
     .msta_rst(msta_rst),
     .mbdr_micro(mbdr_micro[7:0]),
     .mbdr_i2c(mbdr_i2c[7:0]),
     .mbdr_read(mbdr_read));
  //   68000 parallel bus interface
  //   Directional pins
  //   Internal I2C Bus Registers
  //   Address Register (Contains slave address)
  //   Control Register		
  //   Status Register
  //   Data Register
 
endmodule