upcnt4_blk_ver.v

Xilinx的I2C总线控制器

//--------------------------------------------------
//  
//      Verilog code generated by Visual HDL
//
//  Design Unit:
//  ------------
//      Unit    Name  :  upcnt4_blk
//      Library Name  :  i2c_work
//  
//      Creation Date :  Mon Mar 12 10:42:56 2001
//      Version       :  6.7.0 build 17 from Oct  2 2000
//  
//  Options Used:
//  -------------
//      Target
//         HDL        :  Verilog
//         Purpose    :  Synthesis
//         Vendor     :  Design Compiler
//  
//      Style
//         Use Procedures                 :  No
//         Code Destination               :  Combined file
//         Attach Directives              :  Yes
//         Structural                     :  No
//         Preserve spacing for free text :  Yes
//         Sort Ports by mode             :  No
//         Declaration alignment          :  No
//
//--------------------------------------------------
//--------------------------------------------------
//  
//  Library Name :  i2c_work
//  Unit    Name :  upcnt4_blk
//  Unit    Type :  Block Diagram
//  
//----------------------------------------------------
 
module upcnt4 (data, cnt_en, load, clr, clk, qout);
 
  input [3:0] data;        //   Serial data in
  input cnt_en;            //   Count enable
  input load;              //   Load line enable
  input clr;               //   Active low clear
  input clk;               //   Clock
  inout [3:0] qout;
 
  //  constant RESET_ACTIVE : std_logic := '0';
  wire [3:0] q_int;
 
  reg [3:0] visual_0_q_int;
  assign q_int = visual_0_q_int;
 
 
  always @( posedge (clk) or negedge (clr) )
  begin
    //   Clear output register
    if ((!clr))
    begin
      visual_0_q_int <= {{4{ 1'b0 }}};
                           //   On falling edge of clock count
    end
    else
    begin
      //   Load in start value
      if ((load))
      begin
        visual_0_q_int <= data;
                           //   If count enable is high
      end
      else if (cnt_en)
        visual_0_q_int <= q_int + 1;
 
    end
 
  end
 
 
  assign qout = q_int;
 
endmodule