i2c_control_blk_ver.v

Xilinx的I2C总线控制器

//--------------------------------------------------
//  
//      Verilog code generated by Visual HDL
//
//  Design Unit:
//  ------------
//      Unit    Name  :  i2c_control_blk
//      Library Name  :  i2c_work
//  
//      Creation Date :  Mon Mar 12 10:41:54 2001
//      Version       :  6.7.0 build 17 from Oct  2 2000
//  
//  Options Used:
//  -------------
//      Target
//         HDL        :  Verilog
//         Purpose    :  Synthesis
//         Vendor     :  Design Compiler
//  
//      Style
//         Use Procedures                 :  No
//         Code Destination               :  Combined file
//         Attach Directives              :  Yes
//         Structural                     :  No
//         Preserve spacing for free text :  Yes
//         Sort Ports by mode             :  No
//         Declaration alignment          :  No
//
//--------------------------------------------------
//--------------------------------------------------
//  
//  Library Name :  i2c_work
//  Unit    Name :  i2c_control_blk
//  Unit    Type :  Block Diagram
//  
//----------------------------------------------------
 
module i2c_control (sda, scl, txak, msta, msta_rst, rsta, mtx, mbdr_micro,
                        madr, mbb, mcf, maas, mal, srw, mif, rxak, mbdr_i2c,
                        mbcr_wr, mif_bit_reset, mal_bit_reset, sys_clk, reset);
 
  //   I2C bus signals
  inout sda;
  inout scl;
  //   interface signals from uP interface
  input txak;              //   value for acknowledge when xmit
  input msta;              //   master/slave select
  output msta_rst;         //   resets MSTA bit if arbitration is lost
  input rsta;              //   repeated start
  input mtx;               //   master read/write
  input [7:0] mbdr_micro;  //   uP data to output on I2C bus
  input [7:0] madr;        //   I2C slave address
  output mbb;              //   bus busy
  inout mcf;               //   data transfer
  inout maas;              //   addressed as slave
  inout mal;               //   arbitration lost
  inout srw;               //   slave read/write
  output mif;              //   interrupt pending
  output rxak;             //   received acknowledge
  inout [7:0] mbdr_i2c;    //   I2C data for uP
  input mbcr_wr;           //   indicates that MCBR register was written
  input mif_bit_reset;     //   indicates that the MIF bit should be reset
  input mal_bit_reset;     //   indicates that the MAL bit should be reset
  input sys_clk;
  input reset;
 
  `define state_type_IDLE	 3'd0
  `define state_type_HEADER	 3'd1
  `define state_type_ACK_HEADER	 3'd2
  `define state_type_RCV_DATA	 3'd3
  `define state_type_ACK_DATA	 3'd4
  `define state_type_XMIT_DATA	 3'd5
  `define state_type_WAIT_ACK	 3'd6
  `define scl_state_type_SCL_IDLE	 3'd0
  `define scl_state_type_START	 3'd1
  `define scl_state_type_SCL_LOW_EDGE	 3'd2
  `define scl_state_type_SCL_LOW	 3'd3
  `define scl_state_type_SCL_HIGH_EDGE	 3'd4
  `define scl_state_type_SCL_HIGH	 3'd5
  `define CNT_100KHZ	 5'b10100
                           //   number of 2MHz clocks in 100KHz
  `define HIGH_CNT	 4'b1000
                           //   number of 2MHz clocks in half
  //   100KHz period -1 since count from 0
  //   and -1 for "edge" state
  `define LOW_CNT	 4'b1000
                           //   number of 2Mhz clocks in half
  //   100KHZ period -1 since count from 0
  //   and -1 for "edge" state
  `define HIGH_CNT_2	 4'b0100
                           //   half of HIGH_CNT
  `define DATA_HOLD	 4'b0001
                           //   number of 2MHz clocks in 300ns
  `define START_HOLD	 4'b0010
 
  `define CLR_REG	 8'b00000000
 
  `define START_CNT	 4'b0000
 
  `define CNT_DONE	 4'b0111
 
  `define ZERO_CNT	 4'b0000
 
  parameter ZERO = 1'b0;
  parameter RESET_ACTIVE = 1'b0;
  //   Used to check slave address detected
  wire addr_match;
  wire arb_lost;           //   1 if arbitration is lost
  //   Bit counter 0 to 7
  wire [3:0] bit_cnt;
  wire bit_cnt_clr;
  wire bit_cnt_en;
  wire bit_cnt_ld;
  //   from state machine
  wire bus_busy;           //   indicates that the bus is busy - set when START, cleared when STOP
  wire bus_busy_d1;        //   delayed sample of bus busy used to determine MAL
  //   Clock Counter
  wire [3:0] clk_cnt;
  wire clk_cnt_en;
  wire clk_cnt_rst;
  wire [3:0] cnt_start;
  wire [3:0] cnt_zero;
  wire detect_start;       //   indicates that a START condition has been detected
  wire detect_stop;        //   indicates that a STOP condition has been detected
  wire gen_start;          //   indicates that the uP wants to generate a START
  wire gen_stop;           //   indicates that the uP wants to generate a STOP
  wire [7:0] i2c_header;   //   shift register that holds I2C header
  wire i2c_header_en;
  wire i2c_header_ld;
  wire i2c_shiftout;
  wire master_sda;         //   sda value when master
  wire master_slave;       //   1 if master, 0 if slave
  wire msta_d1;            //   delayed sample of msta
  wire [2:0] next_scl_state;
  //   the following signals are only here because Viewlogic's VHDL compiler won't allow a constant
  //   to be used in a component instantiation
  wire [7:0] reg_clr;
  wire rep_start;          //   indicates that the uP wants to generate a repeated START
  wire scl_in;             //   sampled version of scl
  wire scl_not;            //   inverted version of SCL
  wire scl_out;            //   combinatorial scl output from scl generator state machine
  wire scl_out_reg;        //   registered version of SCL_OUT
  wire [2:0] scl_state;
  wire sda_in;             //   sampled version of sda
  wire sda_oe;
  wire sda_out;            //   combinatorial sda output from scl generator state machine
  wire sda_out_reg;        //   registered version of SDA_OUT
  wire sda_out_reg_d1;     //   delayed sda output for arbitration comparison
  wire shift_out;
  //   Shift Register and the controls	
  wire [7:0] shift_reg;    //   shift register that holds I2C data				
  wire shift_reg_en;
  wire shift_reg_ld;
  wire slave_sda;          //   sda value when slave
  wire sm_stop;            //   indicates that a STOP condition needs to be generated
  wire [2:0] state;
  wire stop_scl;           //   signal in SCL state machine indicating a STOP
  wire stop_scl_reg;       //   registered version of STOP_SCL
  wire zero_sig;
 
  reg visual_0_msta_rst;
  assign msta_rst = visual_0_msta_rst;
 
  reg visual_0_arb_lost;
  assign arb_lost = visual_0_arb_lost;
 
  reg [2:0] visual_0_next_scl_state;
  assign next_scl_state = visual_0_next_scl_state;
 
  reg visual_0_clk_cnt_rst;
  assign clk_cnt_rst = visual_0_clk_cnt_rst;
 
  reg visual_0_clk_cnt_en;
  assign clk_cnt_en = visual_0_clk_cnt_en;
 
  reg visual_0_stop_scl;
  assign stop_scl = visual_0_stop_scl;
 
  reg visual_0_sda_out;
  assign sda_out = visual_0_sda_out;
 
  reg visual_0_scl_out;
  assign scl_out = visual_0_scl_out;
 
  reg visual_0_stop_scl_reg;
  assign stop_scl_reg = visual_0_stop_scl_reg;
 
  reg visual_0_scl_out_reg;
  assign scl_out_reg = visual_0_scl_out_reg;
 
  reg visual_0_sda_out_reg;
  assign sda_out_reg = visual_0_sda_out_reg;
 
  reg [2:0] visual_0_scl_state;
  assign scl_state = visual_0_scl_state;
 
  reg visual_0_sda_out_reg_d1;
  assign sda_out_reg_d1 = visual_0_sda_out_reg_d1;
 
  reg visual_0_msta_d1;
  assign msta_d1 = visual_0_msta_d1;
 
  reg visual_0_scl_in;
  assign scl_in = visual_0_scl_in;
 
  reg visual_0_sda_in;
  assign sda_in = visual_0_sda_in;
 
  reg visual_0_master_slave;
  assign master_slave = visual_0_master_slave;
 
  reg visual_0_gen_stop;
  assign gen_stop = visual_0_gen_stop;
 
  reg visual_0_gen_start;
  assign gen_start = visual_0_gen_start;
 
  reg visual_0_sm_stop;
  assign sm_stop = visual_0_sm_stop;
 
  reg [2:0] visual_0_state;
  assign state = visual_0_state;
 
  reg visual_0_detect_start;
  assign detect_start = visual_0_detect_start;
 
  reg visual_0_rxak;
  assign rxak = visual_0_rxak;
 
  reg visual_0_detect_stop;
  assign detect_stop = visual_0_detect_stop;
 
  reg visual_0_i2c_header_en;
  assign i2c_header_en = visual_0_i2c_header_en;
 
  reg visual_0_bus_busy_d1;
  assign bus_busy_d1 = visual_0_bus_busy_d1;
 
  reg visual_0_bus_busy;
  assign bus_busy = visual_0_bus_busy;
 
  reg visual_0_mal;
  assign mal = visual_0_mal;
 
  reg visual_0_maas;
  assign maas = visual_0_maas;
 
  reg visual_0_mcf;
  assign mcf = visual_0_mcf;
 
  reg visual_0_srw;
  assign srw = visual_0_srw;
 
  reg visual_0_shift_reg_ld;
  assign shift_reg_ld = visual_0_shift_reg_ld;
 
  reg visual_0_shift_reg_en;
  assign shift_reg_en = visual_0_shift_reg_en;
 
  reg visual_0_mif;
  assign mif = visual_0_mif;
 
  reg visual_0_slave_sda;
  assign slave_sda = visual_0_slave_sda;
 
  reg visual_0_master_sda;
  assign master_sda = visual_0_master_sda;
 
  reg [7:0] visual_0_mbdr_i2c;
  assign mbdr_i2c = visual_0_mbdr_i2c;
 
 
  //   ************************  Bit Counter  ************************
  upcnt4  BITCNT
    (
     .data(cnt_start[3:0]),
     .cnt_en(bit_cnt_en),
     .load(bit_cnt_ld),
     .clr(reset),
     .clk(scl_not),
     .qout(bit_cnt[3:0]));
 
  //   ************************  Clock Counter Implementation ************************
  //   The following code implements the counter that divides the sys_clock for
  //   creation of SCL. Control lines for this counter are set in SCL state machine
  upcnt4  CLKCNT
    (
     .data(cnt_zero[3:0]),
     .cnt_en(clk_cnt_en),
     .load(clk_cnt_rst),
     .clr(reset),
     .clk(sys_clk),
     .qout(clk_cnt[3:0]));
 
  //   ************************  I2C Header Shift Register ************************
  //   Header/Address Shift Register
  SHIFT8  I2CHEADER_REG
    (
     .clk(scl_not),
     .clr(reset),
     .data_ld(i2c_header_ld),
     .data_in(reg_clr[7:0]),
     .shift_in(sda_in),
     .shift_en(i2c_header_en),
     .shift_out(i2c_shiftout),
     .data_out(i2c_header[7:0]));
 
  //   ************************  I2C Data Shift Register ************************
  SHIFT8  I2CDATA_REG
    (
     .clk(scl_not),
     .clr(reset),
     .data_ld(shift_reg_ld),
     .data_in(mbdr_micro[7:0]),
     .shift_in(sda_in),
     .shift_en(shift_reg_en),
     .shift_out(shift_out),
     .data_out(shift_reg[7:0]));
 
  //   ************************  Arbitration Process ************************
  //   This process checks the master's outgoing SDA with the incoming SDA to determine
  //   if control of the bus has been lost. SDA is checked only when SCL is high
  //   and during the states IDLE, HEADER, and XMIT_DATA to insure that START and STOP
  //   conditions are not set when the bus is busy. Note that this is only done when Master.
  //   When arbitration is lost, a reset is generated for the MSTA bit
  //   Note that when arbitration is lost, the mode is switched to slave and SCL continues
  //   to be generated until the byte transfer is complete
  //   arb_lost stays set until scl state machine goes to IDLE state
  always @( posedge (sys_clk) or negedge (reset) )
  begin
    if (!reset)
    begin
      visual_0_arb_lost <= 1'b0;
      visual_0_msta_rst <= 1'b0;
    end
    else
    begin
      if (scl_state == `scl_state_type_SCL_IDLE)
      begin
        visual_0_arb_lost <= 1'b0;
        visual_0_msta_rst <= 1'b0;
      end
      else if ((master_slave))
        //   only need to check arbitration in master mode
        //   check for SCL high before comparing data and insure that arb_lost is
        //   not already set
        if ((scl_in && scl && !arb_lost && (state == `state_type_HEADER || state
            == `state_type_XMIT_DATA || state == `state_type_IDLE)))
          //   when master, will check bus in all states except ACK_HEADER and WAIT_ACK
          //   this will insure that arb_lost is set if a start or stop condition
          //   is set at the wrong time
          if (sda_out_reg_d1 == sda_in)
          begin
            visual_0_arb_lost <= 1'b0;
            visual_0_msta_rst <= 1'b0;
          end
          else
          begin