shift8_blk_ver.v

Xilinx的I2C总线控制器

//--------------------------------------------------
//  
//      Verilog code generated by Visual HDL
//
//  Design Unit:
//  ------------
//      Unit    Name  :  SHIFT8_blk
//      Library Name  :  i2c_work
//  
//      Creation Date :  Mon Mar 12 10:40:24 2001
//      Version       :  6.7.0 build 17 from Oct  2 2000
//  
//  Options Used:
//  -------------
//      Target
//         HDL        :  Verilog
//         Purpose    :  Synthesis
//         Vendor     :  Design Compiler
//  
//      Style
//         Use Procedures                 :  No
//         Code Destination               :  Combined file
//         Attach Directives              :  Yes
//         Structural                     :  No
//         Preserve spacing for free text :  Yes
//         Sort Ports by mode             :  No
//         Declaration alignment          :  No
//
//--------------------------------------------------
//--------------------------------------------------
//  
//  Library Name :  i2c_work
//  Unit    Name :  SHIFT8_blk
//  Unit    Type :  Block Diagram
//  
//----------------------------------------------------
 
module SHIFT8 (clk, clr, data_ld, data_in, shift_in, shift_en, shift_out,
                   data_out);
 
  input clk;               //   Clock
  input clr;               //   Clear
  input data_ld;           //   Data load enable
  input [7:0] data_in;     //   Data to load in
  input shift_in;          //   Serial data in
  input shift_en;          //   Shift enable
  output shift_out;        //   Shift serial data out
  output [7:0] data_out;   //   Shifted data
 
  //  constant RESET_ACTIVE : std_logic := '0';
  wire [7:0] data_int;
 
  reg [7:0] visual_0_data_int;
  assign data_int = visual_0_data_int;
 
 
  always @( posedge (clk) or negedge (clr) )
  begin
    //   Clear output register
    if ((!clr))
    begin
      visual_0_data_int <= {{8{ 1'b0 }}};
                           //   On rising edge of clock, shift in data
    end
    else
    begin
      //   Load data
      if ((data_ld))
      begin
        visual_0_data_int <= data_in;
                           //   If shift enable is high
      end
      else if (shift_en)
        //   Shift the data
        visual_0_data_int <= {data_int[6:0] , shift_in};
 
    end
 
  end
 
 
  assign shift_out = data_int[7];
  assign data_out = data_int;
 
endmodule