ocmj2x8.map.qmsg

用verilog写的对OCMJ2X8液晶模块控制代码

{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add2 " "Info: Instantiated megafunction \"lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 122 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altshift.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|altshift:result_ext_latency_ffs lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 122 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add2 " "Info: Instantiated megafunction \"lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 122 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|altshift:carry_ext_latency_ffs lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 122 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add2 " "Info: Instantiated megafunction \"lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 122 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 78 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|addcore:adder lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 78 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add1 " "Info: Instantiated megafunction \"lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 78 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "lcd_db\[7\]~reg0 lcd_db\[5\]~reg0 " "Info: Duplicate register \"lcd_db\[7\]~reg0\" merged to single register \"lcd_db\[5\]~reg0\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "lcd_db\[6\]~reg0 lcd_db\[5\]~reg0 " "Info: Duplicate register \"lcd_db\[6\]~reg0\" merged to single register \"lcd_db\[5\]~reg0\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|OCMJ2X8\|mstate 8 " "Info: State machine \"\|OCMJ2X8\|mstate\" contains 8 states" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|OCMJ2X8\|mstate " "Info: Selected Auto state machine encoding method for state machine \"\|OCMJ2X8\|mstate\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|OCMJ2X8\|mstate " "Info: Encoding result for state machine \"\|OCMJ2X8\|mstate\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "8 " "Info: Completed encoding using 8 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mstate.wrdata_c " "Info: Encoded state bit \"mstate.wrdata_c\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mstate.wrdata_b " "Info: Encoded state bit \"mstate.wrdata_b\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mstate.wrdata_a " "Info: Encoded state bit \"mstate.wrdata_a\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mstate.clear_c " "Info: Encoded state bit \"mstate.clear_c\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mstate.clear_b " "Info: Encoded state bit \"mstate.clear_b\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mstate.clear_a " "Info: Encoded state bit \"mstate.clear_a\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mstate.idle " "Info: Encoded state bit \"mstate.idle\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mstate.delay " "Info: Encoded state bit \"mstate.delay\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|OCMJ2X8\|mstate.idle 00000000 " "Info: State \"\|OCMJ2X8\|mstate.idle\" uses code string \"00000000\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|OCMJ2X8\|mstate.clear_a 00000110 " "Info: State \"\|OCMJ2X8\|mstate.clear_a\" uses code string \"00000110\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|OCMJ2X8\|mstate.clear_b 00001010 " "Info: State \"\|OCMJ2X8\|mstate.clear_b\" uses code string \"00001010\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|OCMJ2X8\|mstate.clear_c 00010010 " "Info: State \"\|OCMJ2X8\|mstate.clear_c\" uses code string \"00010010\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|OCMJ2X8\|mstate.wrdata_a 00100010 " "Info: State \"\|OCMJ2X8\|mstate.wrdata_a\" uses code string \"00100010\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|OCMJ2X8\|mstate.wrdata_b 01000010 " "Info: State \"\|OCMJ2X8\|mstate.wrdata_b\" uses code string \"01000010\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|OCMJ2X8\|mstate.wrdata_c 10000010 " "Info: State \"\|OCMJ2X8\|mstate.wrdata_c\" uses code string \"10000010\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|OCMJ2X8\|mstate.delay 00000011 " "Info: State \"\|OCMJ2X8\|mstate.delay\" uses code string \"00000011\"" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 12 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "lcd_db\[3\] GND " "Warning (13410): Pin \"lcd_db\[3\]\" stuck at GND" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 3 " "Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mstate~34 " "Info: Register \"mstate~34\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mstate~35 " "Info: Register \"mstate~35\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mstate~36 " "Info: Register \"mstate~36\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "106 " "Info: Implemented 106 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "94 " "Info: Implemented 94 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Allocated 141 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 20 19:45:08 2008 " "Info: Processing ended: Sun Apr 20 19:45:08 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}