ds1307_lcd.map.rpt

来自「通过IIC总线读写实时时钟DS1307」· RPT 代码 · 共 500 行 · 第 1/4 页

; lcd12864:inst|mstate~30                ; Lost fanout                               ;
; lcd12864:inst|mstate.delay             ; Stuck at GND due to stuck port data_in    ;
; lcd12864:inst|div_cnt[0]               ; Merged with DS1307:inst2|clk_div[0]       ;
; Total Number of Removed Registers = 42 ;                                           ;
+----------------------------------------+-------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                         ;
+-------------------------+---------------------------+-------------------------------------------------------------------------------+
; Register name           ; Reason for Removal        ; Registers Removed due to This Register                                        ;
+-------------------------+---------------------------+-------------------------------------------------------------------------------+
; DS1307:inst2|addr_wr[7] ; Stuck at GND              ; DS1307:inst2|data_buf[7], DS1307:inst2|data_buf[6], DS1307:inst2|data_buf[5], ;
;                         ; due to stuck port data_in ; DS1307:inst2|data_buf[3], DS1307:inst2|data_buf[2], DS1307:inst2|data_buf[1], ;
;                         ;                           ; DS1307:inst2|data_buf[4], DS1307:inst2|writeData_reg[4]                       ;
+-------------------------+---------------------------+-------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 172   ;
; Number of registers using Synchronous Clear  ; 11    ;
; Number of registers using Synchronous Load   ; 11    ;
; Number of registers using Asynchronous Clear ; 117   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 87    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; lcd12864:inst|cnt[3]                   ; 2       ;
; lcd12864:inst|cnt[7]                   ; 2       ;
; DS1307:inst2|scl_xhdl1                 ; 2       ;
; DS1307:inst2|sda_buf                   ; 18      ;
; Total number of inverted registers = 4 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |DS1307_LCD|lcd12864:inst|lcd_cs1        ;
; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DS1307_LCD|lcd12864:inst|column_cnt[7]  ;
; 4:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |DS1307_LCD|lcd12864:inst|cnt[6]         ;
; 6:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; Yes        ; |DS1307_LCD|lcd12864:inst|data[3]        ;
; 12:1               ; 8 bits    ; 64 LEs        ; 0 LEs                ; 64 LEs                 ; Yes        ; |DS1307_LCD|DS1307:inst2|readData_reg[1] ;
; 33:1               ; 2 bits    ; 44 LEs        ; 6 LEs                ; 38 LEs                 ; Yes        ; |DS1307_LCD|DS1307:inst2|main_state[1]   ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |DS1307_LCD|lcd12864:inst|cnt[3]         ;
; 256:1              ; 4 bits    ; 680 LEs       ; 24 LEs               ; 656 LEs                ; No         ; |DS1307_LCD|lcd12864:inst|Selector0      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+


+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lcd12864:inst ;
+----------------+--------+----------------------------------+
; Parameter Name ; Value  ; Type                             ;
+----------------+--------+----------------------------------+
; idle           ; 000000 ; Unsigned Binary                  ;
; setstrow_a     ; 000001 ; Unsigned Binary                  ;
; setstrow_b     ; 000010 ; Unsigned Binary                  ;
; setstrow_c     ; 000011 ; Unsigned Binary                  ;
; lcdon_a        ; 000100 ; Unsigned Binary                  ;
; lcdon_b        ; 000101 ; Unsigned Binary                  ;
; lcdon_c        ; 000110 ; Unsigned Binary                  ;
; clr_str_a      ; 000111 ; Unsigned Binary                  ;
; clr_str_b      ; 001000 ; Unsigned Binary                  ;
; clr_str_c      ; 001001 ; Unsigned Binary                  ;
; clr_stc_a      ; 001010 ; Unsigned Binary                  ;
; clr_stc_b      ; 001011 ; Unsigned Binary                  ;
; clr_stc_c      ; 001100 ; Unsigned Binary                  ;
; clr_dat_a      ; 001101 ; Unsigned Binary                  ;
; clr_dat_b      ; 001110 ; Unsigned Binary                  ;
; clr_dat_c      ; 001111 ; Unsigned Binary                  ;
; setrow_a       ; 010000 ; Unsigned Binary                  ;
; setrow_b       ; 010001 ; Unsigned Binary                  ;
; setrow_c       ; 010010 ; Unsigned Binary                  ;
; setcol_a       ; 010011 ; Unsigned Binary                  ;
; setcol_b       ; 010100 ; Unsigned Binary                  ;
; setcol_c       ; 010101 ; Unsigned Binary                  ;
; dispchar_a     ; 010110 ; Unsigned Binary                  ;
; dispchar_b     ; 010111 ; Unsigned Binary                  ;
; dispchar_c     ; 011000 ; Unsigned Binary                  ;
; delay          ; 101010 ; Unsigned Binary                  ;
; x_offset       ; 50     ; Untyped                          ;
+----------------+--------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Fri Oct 24 13:16:25 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DS1307_LCD -c DS1307_LCD
Info: Found 2 design units, including 1 entities, in source file source/DS1307.vhd
    Info: Found design unit 1: DS1307-translated
    Info: Found entity 1: DS1307
Warning (10236): Verilog HDL Implicit Net warning at lcd12864.v(182): created implicit net for "clk_div"
Info: Found 1 design units, including 1 entities, in source file source/lcd12864.v
    Info: Found entity 1: lcd12864
Info: Found 1 design units, including 1 entities, in source file source/DS1307_LCD.bdf
    Info: Found entity 1: DS1307_LCD
Info: Elaborating entity "DS1307_LCD" for the top level hierarchy
Info: Elaborating entity "DS1307" for hierarchy "DS1307:inst2"
Warning (10036): Verilog HDL or VHDL warning at DS1307.vhd(26): object "cnt_inc" assigned a value but never read
Info: Elaborating entity "lcd12864" for hierarchy "lcd12864:inst"
Warning (10230): Verilog HDL assignment warning at lcd12864.v(177): truncated value with size 16 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at lcd12864.v(179): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at lcd12864.v(208): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at lcd12864.v(269): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at lcd12864.v(298): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at lcd12864.v(318): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at lcd12864.v(342): truncated value with size 32 to match size of target (8)