ds1307_lcd.tan.qmsg

来自「通过IIC总线读写实时时钟DS1307」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "ITDB_TSU_RESULT" "DS1307:inst2\|sda_buf sda clk 11.545 ns register " "Info: tsu for register \"DS1307:inst2\|sda_buf\" (data pin = \"sda\", clock pin = \"clk\") is 11.545 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.434 ns + Longest pin register " "Info: + Longest pin to register delay is 14.434 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_173 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_173; Fanout = 1; PIN Node = 'sda'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 144 384 560 160 "sda" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns sda~0 2 COMB IOC_X25_Y19_N0 4 " "Info: 2: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = IOC_X25_Y19_N0; Fanout = 4; COMB Node = 'sda~0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.964 ns" { sda sda~0 } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 144 384 560 160 "sda" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.186 ns) + CELL(0.623 ns) 7.773 ns DS1307:inst2\|sda_buf~66 3 COMB LCCOMB_X22_Y15_N10 4 " "Info: 3: + IC(6.186 ns) + CELL(0.623 ns) = 7.773 ns; Loc. = LCCOMB_X22_Y15_N10; Fanout = 4; COMB Node = 'DS1307:inst2\|sda_buf~66'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.809 ns" { sda~0 DS1307:inst2|sda_buf~66 } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.206 ns) 8.360 ns DS1307:inst2\|Mux62~733 4 COMB LCCOMB_X22_Y15_N12 1 " "Info: 4: + IC(0.381 ns) + CELL(0.206 ns) = 8.360 ns; Loc. = LCCOMB_X22_Y15_N12; Fanout = 1; COMB Node = 'DS1307:inst2\|Mux62~733'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.587 ns" { DS1307:inst2|sda_buf~66 DS1307:inst2|Mux62~733 } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.206 ns) 8.937 ns DS1307:inst2\|Mux62~734 5 COMB LCCOMB_X22_Y15_N22 1 " "Info: 5: + IC(0.371 ns) + CELL(0.206 ns) = 8.937 ns; Loc. = LCCOMB_X22_Y15_N22; Fanout = 1; COMB Node = 'DS1307:inst2\|Mux62~734'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.577 ns" { DS1307:inst2|Mux62~733 DS1307:inst2|Mux62~734 } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.206 ns) 10.241 ns DS1307:inst2\|Mux62~735 6 COMB LCCOMB_X22_Y12_N14 2 " "Info: 6: + IC(1.098 ns) + CELL(0.206 ns) = 10.241 ns; Loc. = LCCOMB_X22_Y12_N14; Fanout = 2; COMB Node = 'DS1307:inst2\|Mux62~735'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.304 ns" { DS1307:inst2|Mux62~734 DS1307:inst2|Mux62~735 } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.132 ns) + CELL(0.651 ns) 12.024 ns DS1307:inst2\|Mux50~1973 7 COMB LCCOMB_X23_Y13_N0 1 " "Info: 7: + IC(1.132 ns) + CELL(0.651 ns) = 12.024 ns; Loc. = LCCOMB_X23_Y13_N0; Fanout = 1; COMB Node = 'DS1307:inst2\|Mux50~1973'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.783 ns" { DS1307:inst2|Mux62~735 DS1307:inst2|Mux50~1973 } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 280 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.206 ns) 12.608 ns DS1307:inst2\|Mux99~17 8 COMB LCCOMB_X23_Y13_N18 1 " "Info: 8: + IC(0.378 ns) + CELL(0.206 ns) = 12.608 ns; Loc. = LCCOMB_X23_Y13_N18; Fanout = 1; COMB Node = 'DS1307:inst2\|Mux99~17'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.584 ns" { DS1307:inst2|Mux50~1973 DS1307:inst2|Mux99~17 } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 516 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.206 ns) 13.184 ns DS1307:inst2\|Mux99~18 9 COMB LCCOMB_X23_Y13_N28 1 " "Info: 9: + IC(0.370 ns) + CELL(0.206 ns) = 13.184 ns; Loc. = LCCOMB_X23_Y13_N28; Fanout = 1; COMB Node = 'DS1307:inst2\|Mux99~18'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.576 ns" { DS1307:inst2|Mux99~17 DS1307:inst2|Mux99~18 } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 516 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.206 ns) 13.756 ns DS1307:inst2\|Mux127~129 10 COMB LCCOMB_X23_Y13_N6 1 " "Info: 10: + IC(0.366 ns) + CELL(0.206 ns) = 13.756 ns; Loc. = LCCOMB_X23_Y13_N6; Fanout = 1; COMB Node = 'DS1307:inst2\|Mux127~129'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.572 ns" { DS1307:inst2|Mux99~18 DS1307:inst2|Mux127~129 } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 243 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.202 ns) 14.326 ns DS1307:inst2\|Mux127~130 11 COMB LCCOMB_X23_Y13_N16 1 " "Info: 11: + IC(0.368 ns) + CELL(0.202 ns) = 14.326 ns; Loc. = LCCOMB_X23_Y13_N16; Fanout = 1; COMB Node = 'DS1307:inst2\|Mux127~130'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.570 ns" { DS1307:inst2|Mux127~129 DS1307:inst2|Mux127~130 } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 243 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 14.434 ns DS1307:inst2\|sda_buf 12 REG LCFF_X23_Y13_N17 18 " "Info: 12: + IC(0.000 ns) + CELL(0.108 ns) = 14.434 ns; Loc. = LCFF_X23_Y13_N17; Fanout = 18; REG Node = 'DS1307:inst2\|sda_buf'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { DS1307:inst2|Mux127~130 DS1307:inst2|sda_buf } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.784 ns ( 26.22 % ) " "Info: Total cell delay = 3.784 ns ( 26.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.650 ns ( 73.78 % ) " "Info: Total interconnect delay = 10.650 ns ( 73.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "14.434 ns" { sda sda~0 DS1307:inst2|sda_buf~66 DS1307:inst2|Mux62~733 DS1307:inst2|Mux62~734 DS1307:inst2|Mux62~735 DS1307:inst2|Mux50~1973 DS1307:inst2|Mux99~17 DS1307:inst2|Mux99~18 DS1307:inst2|Mux127~129 DS1307:inst2|Mux127~130 DS1307:inst2|sda_buf } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "14.434 ns" { sda {} sda~0 {} DS1307:inst2|sda_buf~66 {} DS1307:inst2|Mux62~733 {} DS1307:inst2|Mux62~734 {} DS1307:inst2|Mux62~735 {} DS1307:inst2|Mux50~1973 {} DS1307:inst2|Mux99~17 {} DS1307:inst2|Mux99~18 {} DS1307:inst2|Mux127~129 {} DS1307:inst2|Mux127~130 {} DS1307:inst2|sda_buf {} } { 0.000ns 0.000ns 6.186ns 0.381ns 0.371ns 1.098ns 1.132ns 0.378ns 0.370ns 0.366ns 0.368ns 0.000ns } { 0.000ns 0.964ns 0.623ns 0.206ns 0.206ns 0.206ns 0.651ns 0.206ns 0.206ns 0.206ns 0.202ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.849 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 5 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 128 -88 80 144 "clk" "" } { 120 80 128 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 76 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 76; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 128 -88 80 144 "clk" "" } { 120 80 128 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.904 ns) + CELL(0.666 ns) 2.849 ns DS1307:inst2\|sda_buf 3 REG LCFF_X23_Y13_N17 18 " "Info: 3: + IC(0.904 ns) + CELL(0.666 ns) = 2.849 ns; Loc. = LCFF_X23_Y13_N17; Fanout = 18; REG Node = 'DS1307:inst2\|sda_buf'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.570 ns" { clk~clkctrl DS1307:inst2|sda_buf } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.39 % ) " "Info: Total cell delay = 1.806 ns ( 63.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.043 ns ( 36.61 % ) " "Info: Total interconnect delay = 1.043 ns ( 36.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.849 ns" { clk clk~clkctrl DS1307:inst2|sda_buf } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.849 ns" { clk {} clk~combout {} clk~clkctrl {} DS1307:inst2|sda_buf {} } { 0.000ns 0.000ns 0.139ns 0.904ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "14.434 ns" { sda sda~0 DS1307:inst2|sda_buf~66 DS1307:inst2|Mux62~733 DS1307:inst2|Mux62~734 DS1307:inst2|Mux62~735 DS1307:inst2|Mux50~1973 DS1307:inst2|Mux99~17 DS1307:inst2|Mux99~18 DS1307:inst2|Mux127~129 DS1307:inst2|Mux127~130 DS1307:inst2|sda_buf } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "14.434 ns" { sda {} sda~0 {} DS1307:inst2|sda_buf~66 {} DS1307:inst2|Mux62~733 {} DS1307:inst2|Mux62~734 {} DS1307:inst2|Mux62~735 {} DS1307:inst2|Mux50~1973 {} DS1307:inst2|Mux99~17 {} DS1307:inst2|Mux99~18 {} DS1307:inst2|Mux127~129 {} DS1307:inst2|Mux127~130 {} DS1307:inst2|sda_buf {} } { 0.000ns 0.000ns 6.186ns 0.381ns 0.371ns 1.098ns 1.132ns 0.378ns 0.370ns 0.366ns 0.368ns 0.000ns } { 0.000ns 0.964ns 0.623ns 0.206ns 0.206ns 0.206ns 0.651ns 0.206ns 0.206ns 0.206ns 0.202ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.849 ns" { clk clk~clkctrl DS1307:inst2|sda_buf } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.849 ns" { clk {} clk~combout {} clk~clkctrl {} DS1307:inst2|sda_buf {} } { 0.000ns 0.000ns 0.139ns 0.904ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[2\] lcd12864:inst\|data\[2\] 15.738 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[2\]\" through register \"lcd12864:inst\|data\[2\]\" is 15.738 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.160 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.160 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 5 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 128 -88 80 144 "clk" "" } { 120 80 128 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.933 ns) + CELL(0.970 ns) 4.043 ns lcd12864:inst\|div_cnt\[7\] 2 REG LCFF_X22_Y11_N31 2 " "Info: 2: + IC(1.933 ns) + CELL(0.970 ns) = 4.043 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'lcd12864:inst\|div_cnt\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.903 ns" { clk lcd12864:inst|div_cnt[7] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.581 ns) + CELL(0.000 ns) 6.624 ns lcd12864:inst\|div_cnt\[7\]~clkctrl 3 COMB CLKCTRL_G3 60 " "Info: 3: + IC(2.581 ns) + CELL(0.000 ns) = 6.624 ns; Loc. = CLKCTRL_G3; Fanout = 60; COMB Node = 'lcd12864:inst\|div_cnt\[7\]~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.581 ns" { lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.870 ns) + CELL(0.666 ns) 8.160 ns lcd12864:inst\|data\[2\] 4 REG LCFF_X24_Y10_N17 2 " "Info: 4: + IC(0.870 ns) + CELL(0.666 ns) = 8.160 ns; Loc. = LCFF_X24_Y10_N17; Fanout = 2; REG Node = 'lcd12864:inst\|data\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.536 ns" { lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|data[2] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 34.02 % ) " "Info: Total cell delay = 2.776 ns ( 34.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.384 ns ( 65.98 % ) " "Info: Total interconnect delay = 5.384 ns ( 65.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.160 ns" { clk lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|data[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.160 ns" { clk {} clk~combout {} lcd12864:inst|div_cnt[7] {} lcd12864:inst|div_cnt[7]~clkctrl {} lcd12864:inst|data[2] {} } { 0.000ns 0.000ns 1.933ns 2.581ns 0.870ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.274 ns + Longest register pin " "Info: + Longest register to pin delay is 7.274 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd12864:inst\|data\[2\] 1 REG LCFF_X24_Y10_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y10_N17; Fanout = 2; REG Node = 'lcd12864:inst\|data\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|data[2] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.018 ns) + CELL(3.256 ns) 7.274 ns data\[2\] 2 PIN PIN_195 0 " "Info: 2: + IC(4.018 ns) + CELL(3.256 ns) = 7.274 ns; Loc. = PIN_195; Fanout = 0; PIN Node = 'data\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.274 ns" { lcd12864:inst|data[2] data[2] } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 224 760 936 240 "data\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.256 ns ( 44.76 % ) " "Info: Total cell delay = 3.256 ns ( 44.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.018 ns ( 55.24 % ) " "Info: Total interconnect delay = 4.018 ns ( 55.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.274 ns" { lcd12864:inst|data[2] data[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.274 ns" { lcd12864:inst|data[2] {} data[2] {} } { 0.000ns 4.018ns } { 0.000ns 3.256ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.160 ns" { clk lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|data[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.160 ns" { clk {} clk~combout {} lcd12864:inst|div_cnt[7] {} lcd12864:inst|div_cnt[7]~clkctrl {} lcd12864:inst|data[2] {} } { 0.000ns 0.000ns 1.933ns 2.581ns 0.870ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.274 ns" { lcd12864:inst|data[2] data[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.274 ns" { lcd12864:inst|data[2] {} data[2] {} } { 0.000ns 4.018ns } { 0.000ns 3.256ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "lcd12864:inst\|data\[2\] rst_n clk 5.028 ns register " "Info: th for register \"lcd12864:inst\|data\[2\]\" (data pin = \"rst_n\", clock pin = \"clk\") is 5.028 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.160 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.160 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 5 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 128 -88 80 144 "clk" "" } { 120 80 128 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.933 ns) + CELL(0.970 ns) 4.043 ns lcd12864:inst\|div_cnt\[7\] 2 REG LCFF_X22_Y11_N31 2 " "Info: 2: + IC(1.933 ns) + CELL(0.970 ns) = 4.043 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'lcd12864:inst\|div_cnt\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.903 ns" { clk lcd12864:inst|div_cnt[7] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.581 ns) + CELL(0.000 ns) 6.624 ns lcd12864:inst\|div_cnt\[7\]~clkctrl 3 COMB CLKCTRL_G3 60 " "Info: 3: + IC(2.581 ns) + CELL(0.000 ns) = 6.624 ns; Loc. = CLKCTRL_G3; Fanout = 60; COMB Node = 'lcd12864:inst\|div_cnt\[7\]~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.581 ns" { lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY