ds1307_lcd.tan.qmsg

来自「通过IIC总线读写实时时钟DS1307」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 128 -88 80 144 "clk" "" } { 120 80 128 136 "clk" "" } } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wr_input_n " "Info: Assuming node \"wr_input_n\" is an undefined clock" {  } { { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 176 -88 80 192 "wr_input_n" "" } } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "wr_input_n" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "DS1307:inst2\|wr_done " "Info: Detected ripple clock \"DS1307:inst2\|wr_done\" as buffer" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 57 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "DS1307:inst2\|wr_done" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "DS1307:inst2\|cnt_div\[22\] " "Info: Detected ripple clock \"DS1307:inst2\|cnt_div\[22\]\" as buffer" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 104 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "DS1307:inst2\|cnt_div\[22\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "DS1307:inst2\|rd_done " "Info: Detected ripple clock \"DS1307:inst2\|rd_done\" as buffer" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 54 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "DS1307:inst2\|rd_done" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd12864:inst\|div_cnt\[7\] " "Info: Detected ripple clock \"lcd12864:inst\|div_cnt\[7\]\" as buffer" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd12864:inst\|div_cnt\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd12864:inst\|column_cnt\[3\] register lcd12864:inst\|data\[3\] 78.25 MHz 12.78 ns Internal " "Info: Clock \"clk\" has Internal fmax of 78.25 MHz between source register \"lcd12864:inst\|column_cnt\[3\]\" and destination register \"lcd12864:inst\|data\[3\]\" (period= 12.78 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.528 ns + Longest register register " "Info: + Longest register to register delay is 12.528 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd12864:inst\|column_cnt\[3\] 1 REG LCFF_X29_Y10_N19 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y10_N19; Fanout = 17; REG Node = 'lcd12864:inst\|column_cnt\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|column_cnt[3] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.813 ns) + CELL(0.647 ns) 1.460 ns lcd12864:inst\|Selector0~1000 2 COMB LCCOMB_X29_Y10_N6 4 " "Info: 2: + IC(0.813 ns) + CELL(0.647 ns) = 1.460 ns; Loc. = LCCOMB_X29_Y10_N6; Fanout = 4; COMB Node = 'lcd12864:inst\|Selector0~1000'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.460 ns" { lcd12864:inst|column_cnt[3] lcd12864:inst|Selector0~1000 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.206 ns) 2.704 ns lcd12864:inst\|Selector2~315 3 COMB LCCOMB_X30_Y10_N20 1 " "Info: 3: + IC(1.038 ns) + CELL(0.206 ns) = 2.704 ns; Loc. = LCCOMB_X30_Y10_N20; Fanout = 1; COMB Node = 'lcd12864:inst\|Selector2~315'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.244 ns" { lcd12864:inst|Selector0~1000 lcd12864:inst|Selector2~315 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.651 ns) 3.752 ns lcd12864:inst\|Selector2~316 4 COMB LCCOMB_X30_Y10_N30 1 " "Info: 4: + IC(0.397 ns) + CELL(0.651 ns) = 3.752 ns; Loc. = LCCOMB_X30_Y10_N30; Fanout = 1; COMB Node = 'lcd12864:inst\|Selector2~316'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.048 ns" { lcd12864:inst|Selector2~315 lcd12864:inst|Selector2~316 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.076 ns) + CELL(0.651 ns) 5.479 ns lcd12864:inst\|Selector2~317 5 COMB LCCOMB_X28_Y10_N4 32 " "Info: 5: + IC(1.076 ns) + CELL(0.651 ns) = 5.479 ns; Loc. = LCCOMB_X28_Y10_N4; Fanout = 32; COMB Node = 'lcd12864:inst\|Selector2~317'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.727 ns" { lcd12864:inst|Selector2~316 lcd12864:inst|Selector2~317 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.370 ns) 6.249 ns lcd12864:inst\|Decoder1~7398 6 COMB LCCOMB_X28_Y10_N18 7 " "Info: 6: + IC(0.400 ns) + CELL(0.370 ns) = 6.249 ns; Loc. = LCCOMB_X28_Y10_N18; Fanout = 7; COMB Node = 'lcd12864:inst\|Decoder1~7398'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.770 ns" { lcd12864:inst|Selector2~317 lcd12864:inst|Decoder1~7398 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.137 ns) + CELL(0.206 ns) 7.592 ns lcd12864:inst\|Decoder1~7410 7 COMB LCCOMB_X26_Y10_N20 2 " "Info: 7: + IC(1.137 ns) + CELL(0.206 ns) = 7.592 ns; Loc. = LCCOMB_X26_Y10_N20; Fanout = 2; COMB Node = 'lcd12864:inst\|Decoder1~7410'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.343 ns" { lcd12864:inst|Decoder1~7398 lcd12864:inst|Decoder1~7410 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.370 ns) 8.359 ns lcd12864:inst\|WideOr10~586 8 COMB LCCOMB_X26_Y10_N0 1 " "Info: 8: + IC(0.397 ns) + CELL(0.370 ns) = 8.359 ns; Loc. = LCCOMB_X26_Y10_N0; Fanout = 1; COMB Node = 'lcd12864:inst\|WideOr10~586'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.767 ns" { lcd12864:inst|Decoder1~7410 lcd12864:inst|WideOr10~586 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.206 ns) 9.663 ns lcd12864:inst\|WideOr10~587 9 COMB LCCOMB_X25_Y12_N24 2 " "Info: 9: + IC(1.098 ns) + CELL(0.206 ns) = 9.663 ns; Loc. = LCCOMB_X25_Y12_N24; Fanout = 2; COMB Node = 'lcd12864:inst\|WideOr10~587'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.304 ns" { lcd12864:inst|WideOr10~586 lcd12864:inst|WideOr10~587 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.370 ns) 10.411 ns lcd12864:inst\|WideOr10~595 10 COMB LCCOMB_X25_Y12_N26 1 " "Info: 10: + IC(0.378 ns) + CELL(0.370 ns) = 10.411 ns; Loc. = LCCOMB_X25_Y12_N26; Fanout = 1; COMB Node = 'lcd12864:inst\|WideOr10~595'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.748 ns" { lcd12864:inst|WideOr10~587 lcd12864:inst|WideOr10~595 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.076 ns) + CELL(0.206 ns) 11.693 ns lcd12864:inst\|WideOr10~596 11 COMB LCCOMB_X24_Y11_N14 1 " "Info: 11: + IC(1.076 ns) + CELL(0.206 ns) = 11.693 ns; Loc. = LCCOMB_X24_Y11_N14; Fanout = 1; COMB Node = 'lcd12864:inst\|WideOr10~596'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.282 ns" { lcd12864:inst|WideOr10~595 lcd12864:inst|WideOr10~596 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.460 ns) 12.528 ns lcd12864:inst\|data\[3\] 12 REG LCFF_X24_Y11_N27 1 " "Info: 12: + IC(0.375 ns) + CELL(0.460 ns) = 12.528 ns; Loc. = LCFF_X24_Y11_N27; Fanout = 1; REG Node = 'lcd12864:inst\|data\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.835 ns" { lcd12864:inst|WideOr10~596 lcd12864:inst|data[3] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.343 ns ( 34.67 % ) " "Info: Total cell delay = 4.343 ns ( 34.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.185 ns ( 65.33 % ) " "Info: Total interconnect delay = 8.185 ns ( 65.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.528 ns" { lcd12864:inst|column_cnt[3] lcd12864:inst|Selector0~1000 lcd12864:inst|Selector2~315 lcd12864:inst|Selector2~316 lcd12864:inst|Selector2~317 lcd12864:inst|Decoder1~7398 lcd12864:inst|Decoder1~7410 lcd12864:inst|WideOr10~586 lcd12864:inst|WideOr10~587 lcd12864:inst|WideOr10~595 lcd12864:inst|WideOr10~596 lcd12864:inst|data[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.528 ns" { lcd12864:inst|column_cnt[3] {} lcd12864:inst|Selector0~1000 {} lcd12864:inst|Selector2~315 {} lcd12864:inst|Selector2~316 {} lcd12864:inst|Selector2~317 {} lcd12864:inst|Decoder1~7398 {} lcd12864:inst|Decoder1~7410 {} lcd12864:inst|WideOr10~586 {} lcd12864:inst|WideOr10~587 {} lcd12864:inst|WideOr10~595 {} lcd12864:inst|WideOr10~596 {} lcd12864:inst|data[3] {} } { 0.000ns 0.813ns 1.038ns 0.397ns 1.076ns 0.400ns 1.137ns 0.397ns 1.098ns 0.378ns 1.076ns 0.375ns } { 0.000ns 0.647ns 0.206ns 0.651ns 0.651ns 0.370ns 0.206ns 0.370ns 0.206ns 0.370ns 0.206ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.012 ns - Smallest " "Info: - Smallest clock skew is 0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.178 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 5 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 128 -88 80 144 "clk" "" } { 120 80 128 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.933 ns) + CELL(0.970 ns) 4.043 ns lcd12864:inst\|div_cnt\[7\] 2 REG LCFF_X22_Y11_N31 2 " "Info: 2: + IC(1.933 ns) + CELL(0.970 ns) = 4.043 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'lcd12864:inst\|div_cnt\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.903 ns" { clk lcd12864:inst|div_cnt[7] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.581 ns) + CELL(0.000 ns) 6.624 ns lcd12864:inst\|div_cnt\[7\]~clkctrl 3 COMB CLKCTRL_G3 60 " "Info: 3: + IC(2.581 ns) + CELL(0.000 ns) = 6.624 ns; Loc. = CLKCTRL_G3; Fanout = 60; COMB Node = 'lcd12864:inst\|div_cnt\[7\]~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.581 ns" { lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.666 ns) 8.178 ns lcd12864:inst\|data\[3\] 4 REG LCFF_X24_Y11_N27 1 " "Info: 4: + IC(0.888 ns) + CELL(0.666 ns) = 8.178 ns; Loc. = LCFF_X24_Y11_N27; Fanout = 1; REG Node = 'lcd12864:inst\|data\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.554 ns" { lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|data[3] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 33.94 % ) " "Info: Total cell delay = 2.776 ns ( 33.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.402 ns ( 66.06 % ) " "Info: Total interconnect delay = 5.402 ns ( 66.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.178 ns" { clk lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|data[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.178 ns" { clk {} clk~combout {} lcd12864:inst|div_cnt[7] {} lcd12864:inst|div_cnt[7]~clkctrl {} lcd12864:inst|data[3] {} } { 0.000ns 0.000ns 1.933ns 2.581ns 0.888ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.166 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.166 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 5 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 128 -88 80 144 "clk" "" } { 120 80 128 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.933 ns) + CELL(0.970 ns) 4.043 ns lcd12864:inst\|div_cnt\[7\] 2 REG LCFF_X22_Y11_N31 2 " "Info: 2: + IC(1.933 ns) + CELL(0.970 ns) = 4.043 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'lcd12864:inst\|div_cnt\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.903 ns" { clk lcd12864:inst|div_cnt[7] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.581 ns) + CELL(0.000 ns) 6.624 ns lcd12864:inst\|div_cnt\[7\]~clkctrl 3 COMB CLKCTRL_G3 60 " "Info: 3: + IC(2.581 ns) + CELL(0.000 ns) = 6.624 ns; Loc. = CLKCTRL_G3; Fanout = 60; COMB Node = 'lcd12864:inst\|div_cnt\[7\]~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.581 ns" { lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.876 ns) + CELL(0.666 ns) 8.166 ns lcd12864:inst\|column_cnt\[3\] 4 REG LCFF_X29_Y10_N19 17 " "Info: 4: + IC(0.876 ns) + CELL(0.666 ns) = 8.166 ns; Loc. = LCFF_X29_Y10_N19; Fanout = 17; REG Node = 'lcd12864:inst\|column_cnt\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.542 ns" { lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|column_cnt[3] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 33.99 % ) " "Info: Total cell delay = 2.776 ns ( 33.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.390 ns ( 66.01 % ) " "Info: Total interconnect delay = 5.390 ns ( 66.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.166 ns" { clk lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|column_cnt[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.166 ns" { clk {} clk~combout {} lcd12864:inst|div_cnt[7] {} lcd12864:inst|div_cnt[7]~clkctrl {} lcd12864:inst|column_cnt[3] {} } { 0.000ns 0.000ns 1.933ns 2.581ns 0.876ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.178 ns" { clk lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|data[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.178 ns" { clk {} clk~combout {} lcd12864:inst|div_cnt[7] {} lcd12864:inst|div_cnt[7]~clkctrl {} lcd12864:inst|data[3] {} } { 0.000ns 0.000ns 1.933ns 2.581ns 0.888ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.166 ns" { clk lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|column_cnt[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.166 ns" { clk {} clk~combout {} lcd12864:inst|div_cnt[7] {} lcd12864:inst|div_cnt[7]~clkctrl {} lcd12864:inst|column_cnt[3] {} } { 0.000ns 0.000ns 1.933ns 2.581ns 0.876ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.528 ns" { lcd12864:inst|column_cnt[3] lcd12864:inst|Selector0~1000 lcd12864:inst|Selector2~315 lcd12864:inst|Selector2~316 lcd12864:inst|Selector2~317 lcd12864:inst|Decoder1~7398 lcd12864:inst|Decoder1~7410 lcd12864:inst|WideOr10~586 lcd12864:inst|WideOr10~587 lcd12864:inst|WideOr10~595 lcd12864:inst|WideOr10~596 lcd12864:inst|data[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.528 ns" { lcd12864:inst|column_cnt[3] {} lcd12864:inst|Selector0~1000 {} lcd12864:inst|Selector2~315 {} lcd12864:inst|Selector2~316 {} lcd12864:inst|Selector2~317 {} lcd12864:inst|Decoder1~7398 {} lcd12864:inst|Decoder1~7410 {} lcd12864:inst|WideOr10~586 {} lcd12864:inst|WideOr10~587 {} lcd12864:inst|WideOr10~595 {} lcd12864:inst|WideOr10~596 {} lcd12864:inst|data[3] {} } { 0.000ns 0.813ns 1.038ns 0.397ns 1.076ns 0.400ns 1.137ns 0.397ns 1.098ns 0.378ns 1.076ns 0.375ns } { 0.000ns 0.647ns 0.206ns 0.651ns 0.651ns 0.370ns 0.206ns 0.370ns 0.206ns 0.370ns 0.206ns 0.460ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.178 ns" { clk lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|data[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.178 ns" { clk {} clk~combout {} lcd12864:inst|div_cnt[7] {} lcd12864:inst|div_cnt[7]~clkctrl {} lcd12864:inst|data[3] {} } { 0.000ns 0.000ns 1.933ns 2.581ns 0.888ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.166 ns" { clk lcd12864:inst|div_cnt[7] lcd12864:inst|div_cnt[7]~clkctrl lcd12864:inst|column_cnt[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.166 ns" { clk {} clk~combout {} lcd12864:inst|div_cnt[7] {} lcd12864:inst|div_cnt[7]~clkctrl {} lcd12864:inst|column_cnt[3] {} } { 0.000ns 0.000ns 1.933ns 2.581ns 0.876ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}