prev_cmp_ds1307_lcd.tan.qmsg

来自「通过IIC总线读写实时时钟DS1307」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "ITAN_NO_REG2REG_EXIST" "wr_input_n " "Info: No valid register-to-register data paths exist for clock \"wr_input_n\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 24 " "Warning: Circuit may not operate. Detected 24 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "DS1307:inst2\|readData_reg\[7\] DS1307:inst2\|out_sec\[7\] clk 2.918 ns " "Info: Found hold time violation between source  pin or register \"DS1307:inst2\|readData_reg\[7\]\" and destination pin or register \"DS1307:inst2\|out_sec\[7\]\" for clock \"clk\" (Hold time is 2.918 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.508 ns + Largest " "Info: + Largest clock skew is 4.508 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.321 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.321 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 5 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 128 -88 80 144 "clk" "" } { 120 80 128 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.854 ns) + CELL(0.970 ns) 3.964 ns DS1307:inst2\|rd_done 2 REG LCFF_X23_Y10_N23 2 " "Info: 2: + IC(1.854 ns) + CELL(0.970 ns) = 3.964 ns; Loc. = LCFF_X23_Y10_N23; Fanout = 2; REG Node = 'DS1307:inst2\|rd_done'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.824 ns" { clk DS1307:inst2|rd_done } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.820 ns) + CELL(0.000 ns) 5.784 ns DS1307:inst2\|rd_done~clkctrl 3 COMB CLKCTRL_G4 27 " "Info: 3: + IC(1.820 ns) + CELL(0.000 ns) = 5.784 ns; Loc. = CLKCTRL_G4; Fanout = 27; COMB Node = 'DS1307:inst2\|rd_done~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.820 ns" { DS1307:inst2|rd_done DS1307:inst2|rd_done~clkctrl } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 7.321 ns DS1307:inst2\|out_sec\[7\] 4 REG LCFF_X26_Y10_N25 2 " "Info: 4: + IC(0.871 ns) + CELL(0.666 ns) = 7.321 ns; Loc. = LCFF_X26_Y10_N25; Fanout = 2; REG Node = 'DS1307:inst2\|out_sec\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { DS1307:inst2|rd_done~clkctrl DS1307:inst2|out_sec[7] } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 37.92 % ) " "Info: Total cell delay = 2.776 ns ( 37.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.545 ns ( 62.08 % ) " "Info: Total interconnect delay = 4.545 ns ( 62.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.321 ns" { clk DS1307:inst2|rd_done DS1307:inst2|rd_done~clkctrl DS1307:inst2|out_sec[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.321 ns" { clk {} clk~combout {} DS1307:inst2|rd_done {} DS1307:inst2|rd_done~clkctrl {} DS1307:inst2|out_sec[7] {} } { 0.000ns 0.000ns 1.854ns 1.820ns 0.871ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.813 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.813 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 5 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 128 -88 80 144 "clk" "" } { 120 80 128 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 76 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 76; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 128 -88 80 144 "clk" "" } { 120 80 128 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.868 ns) + CELL(0.666 ns) 2.813 ns DS1307:inst2\|readData_reg\[7\] 3 REG LCFF_X22_Y10_N21 3 " "Info: 3: + IC(0.868 ns) + CELL(0.666 ns) = 2.813 ns; Loc. = LCFF_X22_Y10_N21; Fanout = 3; REG Node = 'DS1307:inst2\|readData_reg\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.534 ns" { clk~clkctrl DS1307:inst2|readData_reg[7] } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.20 % ) " "Info: Total cell delay = 1.806 ns ( 64.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 35.80 % ) " "Info: Total interconnect delay = 1.007 ns ( 35.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.813 ns" { clk clk~clkctrl DS1307:inst2|readData_reg[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.813 ns" { clk {} clk~combout {} clk~clkctrl {} DS1307:inst2|readData_reg[7] {} } { 0.000ns 0.000ns 0.139ns 0.868ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.321 ns" { clk DS1307:inst2|rd_done DS1307:inst2|rd_done~clkctrl DS1307:inst2|out_sec[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.321 ns" { clk {} clk~combout {} DS1307:inst2|rd_done {} DS1307:inst2|rd_done~clkctrl {} DS1307:inst2|out_sec[7] {} } { 0.000ns 0.000ns 1.854ns 1.820ns 0.871ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.813 ns" { clk clk~clkctrl DS1307:inst2|readData_reg[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.813 ns" { clk {} clk~combout {} clk~clkctrl {} DS1307:inst2|readData_reg[7] {} } { 0.000ns 0.000ns 0.139ns 0.868ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.592 ns - Shortest register register " "Info: - Shortest register to register delay is 1.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DS1307:inst2\|readData_reg\[7\] 1 REG LCFF_X22_Y10_N21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y10_N21; Fanout = 3; REG Node = 'DS1307:inst2\|readData_reg\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { DS1307:inst2|readData_reg[7] } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.132 ns) + CELL(0.460 ns) 1.592 ns DS1307:inst2\|out_sec\[7\] 2 REG LCFF_X26_Y10_N25 2 " "Info: 2: + IC(1.132 ns) + CELL(0.460 ns) = 1.592 ns; Loc. = LCFF_X26_Y10_N25; Fanout = 2; REG Node = 'DS1307:inst2\|out_sec\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { DS1307:inst2|readData_reg[7] DS1307:inst2|out_sec[7] } "NODE_NAME" } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.460 ns ( 28.89 % ) " "Info: Total cell delay = 0.460 ns ( 28.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.132 ns ( 71.11 % ) " "Info: Total interconnect delay = 1.132 ns ( 71.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { DS1307:inst2|readData_reg[7] DS1307:inst2|out_sec[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.592 ns" { DS1307:inst2|readData_reg[7] {} DS1307:inst2|out_sec[7] {} } { 0.000ns 1.132ns } { 0.000ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.321 ns" { clk DS1307:inst2|rd_done DS1307:inst2|rd_done~clkctrl DS1307:inst2|out_sec[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.321 ns" { clk {} clk~combout {} DS1307:inst2|rd_done {} DS1307:inst2|rd_done~clkctrl {} DS1307:inst2|out_sec[7] {} } { 0.000ns 0.000ns 1.854ns 1.820ns 0.871ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.813 ns" { clk clk~clkctrl DS1307:inst2|readData_reg[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.813 ns" { clk {} clk~combout {} clk~clkctrl {} DS1307:inst2|readData_reg[7] {} } { 0.000ns 0.000ns 0.139ns 0.868ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { DS1307:inst2|readData_reg[7] DS1307:inst2|out_sec[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.592 ns" { DS1307:inst2|readData_reg[7] {} DS1307:inst2|out_sec[7] {} } { 0.000ns 1.132ns } { 0.000ns 0.460ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}