ds1307_lcd.hier_info

通过IIC总线读写实时时钟DS1307

|DS1307_LCD
scl <= DS1307:inst2.scl
clk => DS1307:inst2.clk
clk => lcd12864:inst.clk
rst_n => DS1307:inst2.rst_n
rst_n => lcd12864:inst.nrst
cnt_inc_n => DS1307:inst2.cnt_inc_n
wr_input_n => DS1307:inst2.wr_input_n
sda <= DS1307:inst2.sda
lcd_e <= lcd12864:inst.lcd_e
lcd_rs <= lcd12864:inst.lcd_rs
lcd_rw <= lcd12864:inst.lcd_rw
lcd_cs1 <= lcd12864:inst.lcd_cs1
lcd_cs2 <= lcd12864:inst.lcd_cs2
lcd_rst <= lcd12864:inst.lcd_rst
data[0] <= lcd12864:inst.data[0]
data[1] <= lcd12864:inst.data[1]
data[2] <= lcd12864:inst.data[2]
data[3] <= lcd12864:inst.data[3]
data[4] <= lcd12864:inst.data[4]
data[5] <= lcd12864:inst.data[5]
data[6] <= lcd12864:inst.data[6]
data[7] <= lcd12864:inst.data[7]


|DS1307_LCD|DS1307:inst2
clk => cnt_delay[19].CLK
clk => cnt_delay[18].CLK
clk => cnt_delay[17].CLK
clk => cnt_delay[16].CLK
clk => cnt_delay[15].CLK
clk => cnt_delay[14].CLK
clk => cnt_delay[13].CLK
clk => cnt_delay[12].CLK
clk => cnt_delay[11].CLK
clk => cnt_delay[10].CLK
clk => cnt_delay[9].CLK
clk => cnt_delay[8].CLK
clk => cnt_delay[7].CLK
clk => cnt_delay[6].CLK
clk => cnt_delay[5].CLK
clk => cnt_delay[4].CLK
clk => cnt_delay[3].CLK
clk => cnt_delay[2].CLK
clk => cnt_delay[1].CLK
clk => cnt_delay[0].CLK
clk => cnt_div[22].CLK
clk => cnt_div[21].CLK
clk => cnt_div[20].CLK
clk => cnt_div[19].CLK
clk => cnt_div[18].CLK
clk => cnt_div[17].CLK
clk => cnt_div[16].CLK
clk => cnt_div[15].CLK
clk => cnt_div[14].CLK
clk => cnt_div[13].CLK
clk => cnt_div[12].CLK
clk => cnt_div[11].CLK
clk => cnt_div[10].CLK
clk => cnt_div[9].CLK
clk => cnt_div[8].CLK
clk => cnt_div[7].CLK
clk => cnt_div[6].CLK
clk => cnt_div[5].CLK
clk => cnt_div[4].CLK
clk => cnt_div[3].CLK
clk => cnt_div[2].CLK
clk => cnt_div[1].CLK
clk => cnt_div[0].CLK
clk => clk_div[7].CLK
clk => clk_div[6].CLK
clk => clk_div[5].CLK
clk => clk_div[4].CLK
clk => clk_div[3].CLK
clk => clk_div[2].CLK
clk => clk_div[1].CLK
clk => clk_div[0].CLK
clk => phase0.CLK
clk => phase1.CLK
clk => phase2.CLK
clk => phase3.CLK
clk => start_delaycnt.CLK
clk => main_state[1].CLK
clk => main_state[0].CLK
clk => i2c_state[2].CLK
clk => i2c_state[1].CLK
clk => i2c_state[0].CLK
clk => inner_state[3].CLK
clk => inner_state[2].CLK
clk => inner_state[1].CLK
clk => inner_state[0].CLK
clk => scl_xhdl1.CLK
clk => sda_buf.CLK
clk => link.CLK
clk => readData_reg[7].CLK
clk => readData_reg[6].CLK
clk => readData_reg[5].CLK
clk => readData_reg[4].CLK
clk => readData_reg[3].CLK
clk => readData_reg[2].CLK
clk => readData_reg[1].CLK
clk => readData_reg[0].CLK
clk => writeData_reg[7].CLK
clk => writeData_reg[6].CLK
clk => writeData_reg[5].CLK
clk => writeData_reg[4].CLK
clk => writeData_reg[3].CLK
clk => writeData_reg[2].CLK
clk => writeData_reg[1].CLK
clk => writeData_reg[0].CLK
clk => rd_flag.CLK
clk => wr_flag.CLK
clk => rd_done.CLK
clk => wr_done.CLK
rst_n => readData_reg[0].ACLR
rst_n => readData_reg[1].ACLR
rst_n => readData_reg[2].ACLR
rst_n => readData_reg[3].ACLR
rst_n => readData_reg[4].ACLR
rst_n => readData_reg[5].ACLR
rst_n => readData_reg[6].ACLR
rst_n => readData_reg[7].ACLR
rst_n => link.ACLR
rst_n => sda_buf.PRESET
rst_n => scl_xhdl1.PRESET
rst_n => inner_state[0].ACLR
rst_n => inner_state[1].ACLR
rst_n => inner_state[2].ACLR
rst_n => inner_state[3].ACLR
rst_n => i2c_state[0].ACLR
rst_n => i2c_state[1].ACLR
rst_n => i2c_state[2].ACLR
rst_n => main_state[0].ACLR
rst_n => main_state[1].ACLR
rst_n => start_delaycnt.ACLR
rst_n => phase3.ACLR
rst_n => phase2.ACLR
rst_n => phase1.ACLR
rst_n => phase0.ACLR
rst_n => clk_div[0].ACLR
rst_n => clk_div[1].ACLR
rst_n => clk_div[2].ACLR
rst_n => clk_div[3].ACLR
rst_n => clk_div[4].ACLR
rst_n => clk_div[5].ACLR
rst_n => clk_div[6].ACLR
rst_n => clk_div[7].ACLR
rst_n => cnt_div[0].ACLR
rst_n => cnt_div[1].ACLR
rst_n => cnt_div[2].ACLR
rst_n => cnt_div[3].ACLR
rst_n => cnt_div[4].ACLR
rst_n => cnt_div[5].ACLR
rst_n => cnt_div[6].ACLR
rst_n => cnt_div[7].ACLR
rst_n => cnt_div[8].ACLR
rst_n => cnt_div[9].ACLR
rst_n => cnt_div[10].ACLR
rst_n => cnt_div[11].ACLR
rst_n => cnt_div[12].ACLR
rst_n => cnt_div[13].ACLR
rst_n => cnt_div[14].ACLR
rst_n => cnt_div[15].ACLR
rst_n => cnt_div[16].ACLR
rst_n => cnt_div[17].ACLR
rst_n => cnt_div[18].ACLR
rst_n => cnt_div[19].ACLR
rst_n => cnt_div[20].ACLR
rst_n => cnt_div[21].ACLR
rst_n => cnt_div[22].ACLR
rst_n => cnt_delay[0].ACLR
rst_n => cnt_delay[1].ACLR
rst_n => cnt_delay[2].ACLR
rst_n => cnt_delay[3].ACLR
rst_n => cnt_delay[4].ACLR
rst_n => cnt_delay[5].ACLR
rst_n => cnt_delay[6].ACLR
rst_n => cnt_delay[7].ACLR
rst_n => cnt_delay[8].ACLR
rst_n => cnt_delay[9].ACLR
rst_n => cnt_delay[10].ACLR
rst_n => cnt_delay[11].ACLR
rst_n => cnt_delay[12].ACLR
rst_n => cnt_delay[13].ACLR
rst_n => cnt_delay[14].ACLR
rst_n => cnt_delay[15].ACLR
rst_n => cnt_delay[16].ACLR
rst_n => cnt_delay[17].ACLR
rst_n => cnt_delay[18].ACLR
rst_n => cnt_delay[19].ACLR
rst_n => wr_done.ENA
rst_n => writeData_reg[7].ENA
rst_n => writeData_reg[6].ENA
rst_n => writeData_reg[5].ENA
rst_n => writeData_reg[4].ENA
rst_n => writeData_reg[3].ENA
rst_n => writeData_reg[2].ENA
rst_n => writeData_reg[1].ENA
rst_n => writeData_reg[0].ENA
rst_n => rd_flag.ENA
rst_n => wr_flag.ENA
rst_n => rd_done.ENA
cnt_inc_n => ~NO_FANOUT~
wr_input_n => wr_star.CLK
scl <= scl_xhdl1.DB_MAX_OUTPUT_PORT_TYPE
sda <= sda~0
out_sec[0] <= out_sec[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_sec[1] <= out_sec[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_sec[2] <= out_sec[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_sec[3] <= out_sec[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_sec[4] <= out_sec[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_sec[5] <= out_sec[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_sec[6] <= out_sec[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_sec[7] <= out_sec[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_min[0] <= out_min[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_min[1] <= out_min[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_min[2] <= out_min[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_min[3] <= out_min[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_min[4] <= out_min[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_min[5] <= out_min[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_min[6] <= out_min[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_min[7] <= out_min[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_hour[0] <= out_hour[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_hour[1] <= out_hour[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_hour[2] <= out_hour[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_hour[3] <= out_hour[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_hour[4] <= out_hour[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_hour[5] <= out_hour[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_hour[6] <= out_hour[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_hour[7] <= out_hour[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DS1307_LCD|lcd12864:inst
clk => div_cnt[7].CLK
clk => div_cnt[6].CLK
clk => div_cnt[5].CLK
clk => div_cnt[4].CLK
clk => div_cnt[3].CLK
clk => div_cnt[2].CLK
clk => div_cnt[1].CLK
clk => div_cnt[0].CLK
nrst => div_cnt[7].ACLR
nrst => div_cnt[6].ACLR
nrst => div_cnt[5].ACLR
nrst => div_cnt[4].ACLR
nrst => div_cnt[3].ACLR
nrst => div_cnt[2].ACLR
nrst => div_cnt[1].ACLR
nrst => div_cnt[0].ACLR
nrst => cnt[7].PRESET
nrst => cnt[6].ACLR
nrst => cnt[5].ACLR
nrst => cnt[4].ACLR
nrst => cnt[3].PRESET
nrst => cnt[2].ACLR
nrst => cnt[1].ACLR
nrst => cnt[0].ACLR
nrst => col_cnt_buf[0].ENA
nrst => lcd_rs~reg0.ENA
nrst => lcd_e~reg0.ENA
nrst => data[7]~reg0.ENA
nrst => data[6]~reg0.ENA
nrst => data[5]~reg0.ENA
nrst => data[4]~reg0.ENA
nrst => data[3]~reg0.ENA
nrst => data[2]~reg0.ENA
nrst => data[1]~reg0.ENA
nrst => data[0]~reg0.ENA
nrst => lcd_rst~reg0.ENA
nrst => lcd_cs1~reg0.ENA
nrst => lcd_cs2~reg0.ENA
nrst => row_cnt[2].ENA
nrst => row_cnt[1].ENA
nrst => row_cnt[0].ENA
nrst => column_cnt[7].ENA
nrst => column_cnt[6].ENA
nrst => column_cnt[5].ENA
nrst => column_cnt[4].ENA
nrst => column_cnt[3].ENA
nrst => column_cnt[2].ENA
nrst => column_cnt[1].ENA
nrst => column_cnt[0].ENA
nrst => col_cnt_buf[2].ENA
nrst => col_cnt_buf[1].ENA
nrst => mstate~5.IN1
t_sec[0] => Selector3.IN9
t_sec[1] => Selector2.IN9
t_sec[2] => Selector1.IN9
t_sec[3] => Selector0.IN9
t_sec[4] => Selector3.IN8
t_sec[5] => Selector2.IN8
t_sec[6] => Selector1.IN8
t_sec[7] => Selector0.IN8
t_min[0] => Selector3.IN11
t_min[1] => Selector2.IN11
t_min[2] => Selector1.IN11
t_min[3] => Selector0.IN11
t_min[4] => Selector3.IN10
t_min[5] => Selector2.IN10
t_min[6] => Selector1.IN10
t_min[7] => Selector0.IN10
t_hour[0] => Selector3.IN13
t_hour[1] => Selector2.IN13
t_hour[2] => Selector1.IN13
t_hour[3] => Selector0.IN13
t_hour[4] => Selector3.IN12
t_hour[5] => Selector2.IN12
t_hour[6] => Selector1.IN12
t_hour[7] => Selector0.IN12
lcd_e <= lcd_e~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rs <= lcd_rs~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rw <= <GND>
lcd_cs1 <= lcd_cs1~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_cs2 <= lcd_cs2~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rst <= lcd_rst~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE