prev_cmp_ds1307_lcd.map.qmsg

通过IIC总线读写实时时钟DS1307

{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|DS1307_LCD\|lcd12864:inst\|mstate 26 " "Info: State machine \"\|DS1307_LCD\|lcd12864:inst\|mstate\" contains 26 states" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|DS1307_LCD\|lcd12864:inst\|mstate " "Info: Selected Auto state machine encoding method for state machine \"\|DS1307_LCD\|lcd12864:inst\|mstate\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|DS1307_LCD\|lcd12864:inst\|mstate " "Info: Encoding result for state machine \"\|DS1307_LCD\|lcd12864:inst\|mstate\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "26 " "Info: Completed encoding using 26 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.dispchar_c " "Info: Encoded state bit \"lcd12864:inst\|mstate.dispchar_c\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.dispchar_b " "Info: Encoded state bit \"lcd12864:inst\|mstate.dispchar_b\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.dispchar_a " "Info: Encoded state bit \"lcd12864:inst\|mstate.dispchar_a\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.setcol_c " "Info: Encoded state bit \"lcd12864:inst\|mstate.setcol_c\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.setcol_b " "Info: Encoded state bit \"lcd12864:inst\|mstate.setcol_b\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.setcol_a " "Info: Encoded state bit \"lcd12864:inst\|mstate.setcol_a\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.setrow_c " "Info: Encoded state bit \"lcd12864:inst\|mstate.setrow_c\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.setrow_b " "Info: Encoded state bit \"lcd12864:inst\|mstate.setrow_b\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.setrow_a " "Info: Encoded state bit \"lcd12864:inst\|mstate.setrow_a\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.clr_dat_c " "Info: Encoded state bit \"lcd12864:inst\|mstate.clr_dat_c\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.clr_dat_b " "Info: Encoded state bit \"lcd12864:inst\|mstate.clr_dat_b\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.clr_dat_a " "Info: Encoded state bit \"lcd12864:inst\|mstate.clr_dat_a\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.clr_stc_c " "Info: Encoded state bit \"lcd12864:inst\|mstate.clr_stc_c\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.clr_stc_b " "Info: Encoded state bit \"lcd12864:inst\|mstate.clr_stc_b\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.clr_stc_a " "Info: Encoded state bit \"lcd12864:inst\|mstate.clr_stc_a\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.clr_str_c " "Info: Encoded state bit \"lcd12864:inst\|mstate.clr_str_c\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.clr_str_b " "Info: Encoded state bit \"lcd12864:inst\|mstate.clr_str_b\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.clr_str_a " "Info: Encoded state bit \"lcd12864:inst\|mstate.clr_str_a\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.lcdon_c " "Info: Encoded state bit \"lcd12864:inst\|mstate.lcdon_c\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.lcdon_b " "Info: Encoded state bit \"lcd12864:inst\|mstate.lcdon_b\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.lcdon_a " "Info: Encoded state bit \"lcd12864:inst\|mstate.lcdon_a\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.setstrow_c " "Info: Encoded state bit \"lcd12864:inst\|mstate.setstrow_c\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.setstrow_b " "Info: Encoded state bit \"lcd12864:inst\|mstate.setstrow_b\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.setstrow_a " "Info: Encoded state bit \"lcd12864:inst\|mstate.setstrow_a\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.idle " "Info: Encoded state bit \"lcd12864:inst\|mstate.idle\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd12864:inst\|mstate.delay " "Info: Encoded state bit \"lcd12864:inst\|mstate.delay\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.idle 00000000000000000000000000 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.idle\" uses code string \"00000000000000000000000000\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.setstrow_a 00000000000000000000000110 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.setstrow_a\" uses code string \"00000000000000000000000110\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.setstrow_b 00000000000000000000001010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.setstrow_b\" uses code string \"00000000000000000000001010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.setstrow_c 00000000000000000000010010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.setstrow_c\" uses code string \"00000000000000000000010010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.lcdon_a 00000000000000000000100010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.lcdon_a\" uses code string \"00000000000000000000100010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.lcdon_b 00000000000000000001000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.lcdon_b\" uses code string \"00000000000000000001000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.lcdon_c 00000000000000000010000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.lcdon_c\" uses code string \"00000000000000000010000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.clr_str_a 00000000000000000100000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.clr_str_a\" uses code string \"00000000000000000100000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.clr_str_b 00000000000000001000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.clr_str_b\" uses code string \"00000000000000001000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.clr_str_c 00000000000000010000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.clr_str_c\" uses code string \"00000000000000010000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.clr_stc_a 00000000000000100000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.clr_stc_a\" uses code string \"00000000000000100000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.clr_stc_b 00000000000001000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.clr_stc_b\" uses code string \"00000000000001000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.clr_stc_c 00000000000010000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.clr_stc_c\" uses code string \"00000000000010000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.clr_dat_a 00000000000100000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.clr_dat_a\" uses code string \"00000000000100000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.clr_dat_b 00000000001000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.clr_dat_b\" uses code string \"00000000001000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.clr_dat_c 00000000010000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.clr_dat_c\" uses code string \"00000000010000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.setrow_a 00000000100000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.setrow_a\" uses code string \"00000000100000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.setrow_b 00000001000000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.setrow_b\" uses code string \"00000001000000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.setrow_c 00000010000000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.setrow_c\" uses code string \"00000010000000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.setcol_a 00000100000000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.setcol_a\" uses code string \"00000100000000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.setcol_b 00001000000000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.setcol_b\" uses code string \"00001000000000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.setcol_c 00010000000000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.setcol_c\" uses code string \"00010000000000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.dispchar_a 00100000000000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.dispchar_a\" uses code string \"00100000000000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.dispchar_b 01000000000000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.dispchar_b\" uses code string \"01000000000000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.dispchar_c 10000000000000000000000010 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.dispchar_c\" uses code string \"10000000000000000000000010\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DS1307_LCD\|lcd12864:inst\|mstate.delay 00000000000000000000000011 " "Info: State \"\|DS1307_LCD\|lcd12864:inst\|mstate.delay\" uses code string \"00000000000000000000000011\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0}  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lcd12864:inst\|mstate.delay data_in GND " "Warning (14130): Reduced register \"lcd12864:inst\|mstate.delay\" with stuck data_in port to stuck value GND" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 16 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "lcd12864:inst\|div_cnt\[0\] DS1307:inst2\|clk_div\[0\] " "Info (13350): Duplicate register \"lcd12864:inst\|div_cnt\[0\]\" merged to single register \"DS1307:inst2\|clk_div\[0\]\"" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 179 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } } { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 31 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "lcd_rw GND " "Warning (13410): Pin \"lcd_rw\" is stuck at GND" {  } { { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 160 760 936 176 "lcd_rw" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "5 5 " "Info: 5 registers lost all their fanouts during netlist optimizations. The first 5 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd12864:inst\|mstate~26 " "Info: Register \"lcd12864:inst\|mstate~26\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd12864:inst\|mstate~27 " "Info: Register \"lcd12864:inst\|mstate~27\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd12864:inst\|mstate~28 " "Info: Register \"lcd12864:inst\|mstate~28\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd12864:inst\|mstate~29 " "Info: Register \"lcd12864:inst\|mstate~29\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd12864:inst\|mstate~30 " "Info: Register \"lcd12864:inst\|mstate~30\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "cnt_inc_n " "Warning (15610): No output dependent on input pin \"cnt_inc_n\"" {  } { { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 160 -88 80 176 "cnt_inc_n" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "557 " "Info: Implemented 557 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "537 " "Info: Implemented 537 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 39 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 39 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "182 " "Info: Peak virtual memory: 182 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 24 13:06:09 2008 " "Info: Processing ended: Fri Oct 24 13:06:09 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Info: Total CPU time (on all processors): 00:00:13" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}