prev_cmp_ds1307_lcd.map.qmsg

通过IIC总线读写实时时钟DS1307

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_wr\[5\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_wr\[5\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_wr\[4\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_wr\[4\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_wr\[3\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_wr\[3\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_wr\[2\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_wr\[2\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|data_buf\[7\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|data_buf\[7\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|data_buf\[6\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|data_buf\[6\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|data_buf\[5\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|data_buf\[5\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|data_buf\[3\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|data_buf\[3\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|data_buf\[2\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|data_buf\[2\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|data_buf\[1\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|data_buf\[1\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|cnt_div\[0\] lcd12864:inst\|div_cnt\[0\] " "Info (13350): Duplicate register \"DS1307:inst2\|cnt_div\[0\]\" merged to single register \"lcd12864:inst\|div_cnt\[0\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 106 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|data_buf\[0\] DS1307:inst2\|data_buf\[4\] " "Info (13350): Duplicate register \"DS1307:inst2\|data_buf\[0\]\" merged to single register \"DS1307:inst2\|data_buf\[4\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|writeData_reg\[6\] DS1307:inst2\|writeData_reg\[7\] " "Info (13350): Duplicate register \"DS1307:inst2\|writeData_reg\[6\]\" merged to single register \"DS1307:inst2\|writeData_reg\[7\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|writeData_reg\[5\] DS1307:inst2\|writeData_reg\[7\] " "Info (13350): Duplicate register \"DS1307:inst2\|writeData_reg\[5\]\" merged to single register \"DS1307:inst2\|writeData_reg\[7\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|writeData_reg\[3\] DS1307:inst2\|writeData_reg\[7\] " "Info (13350): Duplicate register \"DS1307:inst2\|writeData_reg\[3\]\" merged to single register \"DS1307:inst2\|writeData_reg\[7\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|writeData_reg\[1\] DS1307:inst2\|writeData_reg\[7\] " "Info (13350): Duplicate register \"DS1307:inst2\|writeData_reg\[1\]\" merged to single register \"DS1307:inst2\|writeData_reg\[7\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|writeData_reg\[2\] DS1307:inst2\|writeData_reg\[7\] " "Info (13350): Duplicate register \"DS1307:inst2\|writeData_reg\[2\]\" merged to single register \"DS1307:inst2\|writeData_reg\[7\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|cnt_div\[1\] lcd12864:inst\|div_cnt\[1\] " "Info (13350): Duplicate register \"DS1307:inst2\|cnt_div\[1\]\" merged to single register \"lcd12864:inst\|div_cnt\[1\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 106 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|writeData_reg\[0\] DS1307:inst2\|writeData_reg\[4\] " "Info (13350): Duplicate register \"DS1307:inst2\|writeData_reg\[0\]\" merged to single register \"DS1307:inst2\|writeData_reg\[4\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|cnt_div\[2\] lcd12864:inst\|div_cnt\[2\] " "Info (13350): Duplicate register \"DS1307:inst2\|cnt_div\[2\]\" merged to single register \"lcd12864:inst\|div_cnt\[2\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 106 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|cnt_div\[3\] lcd12864:inst\|div_cnt\[3\] " "Info (13350): Duplicate register \"DS1307:inst2\|cnt_div\[3\]\" merged to single register \"lcd12864:inst\|div_cnt\[3\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 106 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|cnt_div\[4\] lcd12864:inst\|div_cnt\[4\] " "Info (13350): Duplicate register \"DS1307:inst2\|cnt_div\[4\]\" merged to single register \"lcd12864:inst\|div_cnt\[4\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 106 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|cnt_div\[5\] lcd12864:inst\|div_cnt\[5\] " "Info (13350): Duplicate register \"DS1307:inst2\|cnt_div\[5\]\" merged to single register \"lcd12864:inst\|div_cnt\[5\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 106 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DS1307:inst2\|cnt_div\[6\] lcd12864:inst\|div_cnt\[6\] " "Info (13350): Duplicate register \"DS1307:inst2\|cnt_div\[6\]\" merged to single register \"lcd12864:inst\|div_cnt\[6\]\"" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 106 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|writeData_reg\[7\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|writeData_reg\[7\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG_PWRUP_DC" "DS1307:inst2\|data_buf\[4\] data_in VCC " "Warning (14131): Reduced register \"DS1307:inst2\|data_buf\[4\]\" with stuck data_in port to stuck value VCC -- power-up level has changed" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14131 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s! -- power-up level has changed" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG_PWRUP_DC" "DS1307:inst2\|writeData_reg\[4\] data_in VCC " "Warning (14131): Reduced register \"DS1307:inst2\|writeData_reg\[4\]\" with stuck data_in port to stuck value VCC -- power-up level has changed" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 249 -1 0 } }  } 0 14131 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s! -- power-up level has changed" 0 0 "" 0 0}