prev_cmp_ds1307_lcd.map.qmsg

来自「通过IIC总线读写实时时钟DS1307」· QMSG 代码 · 共 58 行 · 第 1/4 页

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 lcd12864.v(298) " "Warning (10230): Verilog HDL assignment warning at lcd12864.v(298): truncated value with size 32 to match size of target (8)" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 298 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 lcd12864.v(318) " "Warning (10230): Verilog HDL assignment warning at lcd12864.v(318): truncated value with size 32 to match size of target (8)" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 318 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 lcd12864.v(342) " "Warning (10230): Verilog HDL assignment warning at lcd12864.v(342): truncated value with size 32 to match size of target (8)" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 342 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 lcd12864.v(347) " "Warning (10230): Verilog HDL assignment warning at lcd12864.v(347): truncated value with size 32 to match size of target (8)" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 347 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 lcd12864.v(369) " "Warning (10230): Verilog HDL assignment warning at lcd12864.v(369): truncated value with size 32 to match size of target (3)" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 369 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 lcd12864.v(375) " "Warning (10230): Verilog HDL assignment warning at lcd12864.v(375): truncated value with size 32 to match size of target (8)" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 375 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 lcd12864.v(397) " "Warning (10230): Verilog HDL assignment warning at lcd12864.v(397): truncated value with size 32 to match size of target (8)" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 397 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_rd\[7\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_rd\[7\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_rd\[6\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_rd\[6\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_rd\[5\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_rd\[5\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_rd\[4\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_rd\[4\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_rd\[3\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_rd\[3\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_rd\[2\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_rd\[2\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_wr\[7\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_wr\[7\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DS1307:inst2\|addr_wr\[6\] data_in GND " "Warning (14130): Reduced register \"DS1307:inst2\|addr_wr\[6\]\" with stuck data_in port to stuck value GND" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 172 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}