prev_cmp_ds1307_lcd.fit.qmsg

通过IIC总线读写实时时钟DS1307

{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 0}  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "rd_input_n " "Warning: Node \"rd_input_n\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "rd_input_n" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 0}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "12.555 ns register register " "Info: Estimated most critical path is register to register delay of 12.555 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd12864:inst\|column_cnt\[5\] 1 REG LAB_X29_Y10 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X29_Y10; Fanout = 18; REG Node = 'lcd12864:inst\|column_cnt\[5\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|column_cnt[5] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.390 ns) + CELL(0.206 ns) 1.596 ns lcd12864:inst\|Selector0~1003 2 COMB LAB_X29_Y11 1 " "Info: 2: + IC(1.390 ns) + CELL(0.206 ns) = 1.596 ns; Loc. = LAB_X29_Y11; Fanout = 1; COMB Node = 'lcd12864:inst\|Selector0~1003'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { lcd12864:inst|column_cnt[5] lcd12864:inst|Selector0~1003 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.206 ns) 3.502 ns lcd12864:inst\|Selector0~1004 3 COMB LAB_X25_Y10 1 " "Info: 3: + IC(1.700 ns) + CELL(0.206 ns) = 3.502 ns; Loc. = LAB_X25_Y10; Fanout = 1; COMB Node = 'lcd12864:inst\|Selector0~1004'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.906 ns" { lcd12864:inst|Selector0~1003 lcd12864:inst|Selector0~1004 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 4.313 ns lcd12864:inst\|Selector0~1005 4 COMB LAB_X25_Y10 1 " "Info: 4: + IC(0.605 ns) + CELL(0.206 ns) = 4.313 ns; Loc. = LAB_X25_Y10; Fanout = 1; COMB Node = 'lcd12864:inst\|Selector0~1005'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { lcd12864:inst|Selector0~1004 lcd12864:inst|Selector0~1005 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 5.124 ns lcd12864:inst\|Selector0~1006 5 COMB LAB_X25_Y10 10 " "Info: 5: + IC(0.605 ns) + CELL(0.206 ns) = 5.124 ns; Loc. = LAB_X25_Y10; Fanout = 10; COMB Node = 'lcd12864:inst\|Selector0~1006'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { lcd12864:inst|Selector0~1005 lcd12864:inst|Selector0~1006 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.651 ns) 5.935 ns lcd12864:inst\|Selector0~1007 6 COMB LAB_X25_Y10 25 " "Info: 6: + IC(0.160 ns) + CELL(0.651 ns) = 5.935 ns; Loc. = LAB_X25_Y10; Fanout = 25; COMB Node = 'lcd12864:inst\|Selector0~1007'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { lcd12864:inst|Selector0~1006 lcd12864:inst|Selector0~1007 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.646 ns) 7.048 ns lcd12864:inst\|Decoder1~7410 7 COMB LAB_X26_Y10 2 " "Info: 7: + IC(0.467 ns) + CELL(0.646 ns) = 7.048 ns; Loc. = LAB_X26_Y10; Fanout = 2; COMB Node = 'lcd12864:inst\|Decoder1~7410'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.113 ns" { lcd12864:inst|Selector0~1007 lcd12864:inst|Decoder1~7410 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 7.859 ns lcd12864:inst\|WideOr10~586 8 COMB LAB_X26_Y10 1 " "Info: 8: + IC(0.441 ns) + CELL(0.370 ns) = 7.859 ns; Loc. = LAB_X26_Y10; Fanout = 1; COMB Node = 'lcd12864:inst\|WideOr10~586'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { lcd12864:inst|Decoder1~7410 lcd12864:inst|WideOr10~586 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.886 ns) + CELL(0.650 ns) 9.395 ns lcd12864:inst\|WideOr10~587 9 COMB LAB_X25_Y12 2 " "Info: 9: + IC(0.886 ns) + CELL(0.650 ns) = 9.395 ns; Loc. = LAB_X25_Y12; Fanout = 2; COMB Node = 'lcd12864:inst\|WideOr10~587'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.536 ns" { lcd12864:inst|WideOr10~586 lcd12864:inst|WideOr10~587 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.650 ns) 10.205 ns lcd12864:inst\|WideOr10~595 10 COMB LAB_X25_Y12 1 " "Info: 10: + IC(0.160 ns) + CELL(0.650 ns) = 10.205 ns; Loc. = LAB_X25_Y12; Fanout = 1; COMB Node = 'lcd12864:inst\|WideOr10~595'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.810 ns" { lcd12864:inst|WideOr10~587 lcd12864:inst|WideOr10~595 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.321 ns) + CELL(0.206 ns) 11.732 ns lcd12864:inst\|WideOr10~596 11 COMB LAB_X24_Y11 1 " "Info: 11: + IC(1.321 ns) + CELL(0.206 ns) = 11.732 ns; Loc. = LAB_X24_Y11; Fanout = 1; COMB Node = 'lcd12864:inst\|WideOr10~596'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { lcd12864:inst|WideOr10~595 lcd12864:inst|WideOr10~596 } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.460 ns) 12.555 ns lcd12864:inst\|data\[3\] 12 REG LAB_X24_Y11 1 " "Info: 12: + IC(0.363 ns) + CELL(0.460 ns) = 12.555 ns; Loc. = LAB_X24_Y11; Fanout = 1; REG Node = 'lcd12864:inst\|data\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.823 ns" { lcd12864:inst|WideOr10~596 lcd12864:inst|data[3] } "NODE_NAME" } } { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.457 ns ( 35.50 % ) " "Info: Total cell delay = 4.457 ns ( 35.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.098 ns ( 64.50 % ) " "Info: Total interconnect delay = 8.098 ns ( 64.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.555 ns" { lcd12864:inst|column_cnt[5] lcd12864:inst|Selector0~1003 lcd12864:inst|Selector0~1004 lcd12864:inst|Selector0~1005 lcd12864:inst|Selector0~1006 lcd12864:inst|Selector0~1007 lcd12864:inst|Decoder1~7410 lcd12864:inst|WideOr10~586 lcd12864:inst|WideOr10~587 lcd12864:inst|WideOr10~595 lcd12864:inst|WideOr10~596 lcd12864:inst|data[3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}