prev_cmp_ds1307_lcd.fit.qmsg

通过IIC总线读写实时时钟DS1307

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "lcd12864:inst\|div_cnt\[7\]  " "Info: Automatically promoted node lcd12864:inst\|div_cnt\[7\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|div_cnt\[7\]~56 " "Info: Destination node lcd12864:inst\|div_cnt\[7\]~56" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|div_cnt[7]~56 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 18 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|div_cnt[7] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DS1307:inst2\|rd_done  " "Info: Automatically promoted node DS1307:inst2\|rd_done " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DS1307:inst2\|rd_done~196 " "Info: Destination node DS1307:inst2\|rd_done~196" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 54 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { DS1307:inst2|rd_done~196 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 54 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { DS1307:inst2|rd_done } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DS1307:inst2\|wr_done  " "Info: Automatically promoted node DS1307:inst2\|wr_done " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DS1307:inst2\|wr_done~154 " "Info: Destination node DS1307:inst2\|wr_done~154" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 57 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { DS1307:inst2|wr_done~154 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 57 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { DS1307:inst2|wr_done } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n (placed in PIN 132 (CLK4, LVDSCLK2p, Input)) " "Info: Automatically promoted node rst_n (placed in PIN 132 (CLK4, LVDSCLK2p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G6 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|lcd_e " "Info: Destination node lcd12864:inst\|lcd_e" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 6 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|lcd_e } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|data\[6\] " "Info: Destination node lcd12864:inst\|data\[6\]" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|data[6] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|data\[2\] " "Info: Destination node lcd12864:inst\|data\[2\]" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|data[2] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|data\[1\] " "Info: Destination node lcd12864:inst\|data\[1\]" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|data[1] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|data\[0\] " "Info: Destination node lcd12864:inst\|data\[0\]" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|data[0] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|lcd_rs " "Info: Destination node lcd12864:inst\|lcd_rs" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 6 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|lcd_rs } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|data\[7\] " "Info: Destination node lcd12864:inst\|data\[7\]" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|data[7] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|lcd_cs1~23 " "Info: Destination node lcd12864:inst\|lcd_cs1~23" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 6 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|lcd_cs1~23 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|lcd_rst~77 " "Info: Destination node lcd12864:inst\|lcd_rst~77" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 6 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|lcd_rst~77 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd12864:inst\|col_cnt_buf\[1\] " "Info: Destination node lcd12864:inst\|col_cnt_buf\[1\]" {  } { { "source/lcd12864.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/lcd12864.v" 195 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd12864:inst|col_cnt_buf[1] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/80/quartus/bin/pin_planner.ppl" { rst_n } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "source/DS1307_LCD.bdf" "" { Schematic "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307_LCD.bdf" { { 144 -88 80 160 "rst_n" "" } } } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DS1307:inst2\|rd_star  " "Info: Automatically promoted node DS1307:inst2\|rd_star " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DS1307:inst2\|out_sec\[5\]~48 " "Info: Destination node DS1307:inst2\|out_sec\[5\]~48" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { DS1307:inst2|out_sec[5]~48 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DS1307:inst2\|out_min\[1\]~43 " "Info: Destination node DS1307:inst2\|out_min\[1\]~43" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { DS1307:inst2|out_min[1]~43 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DS1307:inst2\|out_hour\[5\]~68 " "Info: Destination node DS1307:inst2\|out_hour\[5\]~68" {  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 124 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { DS1307:inst2|out_hour[5]~68 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 53 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { DS1307:inst2|rd_star } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DS1307:inst2\|wr_star  " "Info: Automatically promoted node DS1307:inst2\|wr_star " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0}  } { { "source/DS1307.vhd" "" { Text "E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/source/DS1307.vhd" 56 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { DS1307:inst2|wr_star } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 0}