ds1307_lcd.fit.rpt

通过IIC总线读写实时时钟DS1307

; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Fitter Partition Preservation Settings                                                                 ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Name ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used      ; Hierarchy ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Top  ; 0                 ; 676     ; Placement and Routing        ; Post-Synthesis Netlist ;           ;
+------+-------------------+---------+------------------------------+------------------------+-----------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/Mywork/EDA/Altera/FPGA/CYCII_VC33/DS1307_LCD/DS1307_LCD.pin.


+---------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                             ;
+---------------------------------------------+-----------------------------+
; Resource                                    ; Usage                       ;
+---------------------------------------------+-----------------------------+
; Total logic elements                        ; 513 / 8,256 ( 6 % )         ;
;     -- Combinational with no register       ; 341                         ;
;     -- Register only                        ; 27                          ;
;     -- Combinational with a register        ; 145                         ;
;                                             ;                             ;
; Logic element usage by number of LUT inputs ;                             ;
;     -- 4 input functions                    ; 268                         ;
;     -- 3 input functions                    ; 78                          ;
;     -- <=2 input functions                  ; 140                         ;
;     -- Register only                        ; 27                          ;
;                                             ;                             ;
; Logic elements by mode                      ;                             ;
;     -- normal mode                          ; 407                         ;
;     -- arithmetic mode                      ; 79                          ;
;                                             ;                             ;
; Total registers*                            ; 172 / 8,646 ( 2 % )         ;
;     -- Dedicated logic registers            ; 172 / 8,256 ( 2 % )         ;
;     -- I/O registers                        ; 0 / 390 ( 0 % )             ;
;                                             ;                             ;
; Total LABs:  partially or completely used   ; 42 / 516 ( 8 % )            ;
; User inserted logic elements                ; 0                           ;
; Virtual pins                                ; 0                           ;
; I/O pins                                    ; 20 / 138 ( 14 % )           ;
;     -- Clock pins                           ; 3 / 4 ( 75 % )              ;
; Global signals                              ; 7                           ;
; M4Ks                                        ; 0 / 36 ( 0 % )              ;
; Total memory bits                           ; 0 / 165,888 ( 0 % )         ;
; Total RAM block bits                        ; 0 / 165,888 ( 0 % )         ;
; Embedded Multiplier 9-bit elements          ; 0 / 36 ( 0 % )              ;
; PLLs                                        ; 0 / 2 ( 0 % )               ;
; Global clocks                               ; 7 / 8 ( 88 % )              ;
; JTAGs                                       ; 0 / 1 ( 0 % )               ;
; Average interconnect usage (total/H/V)      ; 1% / 1% / 1%                ;
; Peak interconnect usage (total/H/V)         ; 5% / 6% / 5%                ;
; Maximum fan-out node                        ; rst_n~clkctrl               ;
; Maximum fan-out                             ; 109                         ;
; Highest non-global fan-out signal           ; lcd12864:inst|Selector1~277 ;
; Highest non-global fan-out                  ; 37                          ;
; Total fan-out                               ; 2188                        ;
; Average fan-out                             ; 3.10                        ;
+---------------------------------------------+-----------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                       ;
+------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk        ; 23    ; 1        ; 0            ; 9            ; 0           ; 5                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; cnt_inc_n  ; 102   ; 4        ; 32           ; 0            ; 2           ; 0                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; rst_n      ; 132   ; 3        ; 34           ; 10           ; 0           ; 22                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;