ds1307_lcd.fit.rpt

通过IIC总线读写实时时钟DS1307

Fitter report for DS1307_LCD
Fri Oct 24 13:16:51 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Partition Preservation Settings
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. Bidir Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. Output Pin Default Load For Reported TCO
 13. Fitter Resource Utilization by Entity
 14. Delay Chain Summary
 15. Pad To Core Delay Chain Fanout
 16. Control Signals
 17. Global & Other Fast Signals
 18. Non-Global High Fan-Out Signals
 19. Interconnect Usage Summary
 20. LAB Logic Elements
 21. LAB-wide Signals
 22. LAB Signals Sourced
 23. LAB Signals Sourced Out
 24. LAB Distinct Inputs
 25. Fitter Device Options
 26. Operating Settings and Conditions
 27. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Fitter Summary                                                               ;
+------------------------------------+-----------------------------------------+
; Fitter Status                      ; Successful - Fri Oct 24 13:16:50 2008   ;
; Quartus II Version                 ; 8.0 Build 215 05/29/2008 SJ Web Edition ;
; Revision Name                      ; DS1307_LCD                              ;
; Top-level Entity Name              ; DS1307_LCD                              ;
; Family                             ; Cyclone II                              ;
; Device                             ; EP2C8Q208C8                             ;
; Timing Models                      ; Final                                   ;
; Total logic elements               ; 513 / 8,256 ( 6 % )                     ;
;     Total combinational functions  ; 486 / 8,256 ( 6 % )                     ;
;     Dedicated logic registers      ; 172 / 8,256 ( 2 % )                     ;
; Total registers                    ; 172                                     ;
; Total pins                         ; 20 / 138 ( 14 % )                       ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 0 / 165,888 ( 0 % )                     ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % )                          ;
; Total PLLs                         ; 0 / 2 ( 0 % )                           ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP2C8Q208C8                    ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Device I/O Standard                                                ; 3.3-V LVTTL                    ;                                ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;