usage

主要用于时序分析,无论是ASIC还是FPGA以及DSP都很有效的.欢迎大家使用

NAME
    CTune - ClockTune (v0.9)

SYNOPSIS
    CTune [number of cells/input file name] [output file]
            ([0/default:elmore delay 1:linear delay]) ([w_min] [w_max])

DESCRIPTION
    CTune takes an input file or randomly generate sink loads, then construct
    the clock tree using BB+DME algorithm.  CTune takes five parameters; the 
    first two are mandatory while the last three are optional.

    [number of cells/input file name]
        The first parameter can be an integer number or a file name.  If the
        user supplies a number, CTune will randomly generate sink nodes with
        the capacitance load ranging from 3e-14 to 8e-14 F.  The position of
        the sinks will be within a square of 7000um by 7000um.  User can also
        try the input files r1.pin ~ r5.pin.  These are the same input files
        used in the original DME paper. Users can also create their own input
        files, provided they comply	with the file format.
  
    [output file]
        The second parameter is the output file name for the result.  The
        output is in postscript format.
  
    ([0/default:elmore delay 1:linear delay])
        The third parameter defines the delay model used in the DME algorithm.
        Although this parameter is optional, users have to specify it if they
        want to specify the following parameters.
  
    ([w_min] [w_max])
        The fourth and fifth parameters defines the lower and upper bound of
        the wire width.  The default values, w_min=0.5 and w_max=2.5, are
        used.  They are of no effect in the current version.

NOTE
	The unit length resistance (0.03 Ohm/um) and unit area capacitance
	(2.0e-16 F/um^2) is hard-wired into the program.
	
    The implementation details such as how to break tie are not described in 
    the original paper, thus the results from CTune is slightly different
    from the results reported in the paper.