8-bit.vhd

最基本的vhdl運算

--Binary Multiplier with n=8: VHDL Description
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity binary_multiplier is
  port(CLK,RESET,G,LOADB,LOADQ:in std_logic;
       MULT_BIN:in std_logic_vector(7 downto 0);
       MULT_QIN:in std_logic_vector(7 downto 0);
       MULT_OUT:out std_logic_vector(15 downto 0));
end binary_multiplier;

architecture behavior_8 of binary_multiplier is
  type state_type is (IDLE,MUL0,MUL1);
  signal state,next_state:state_type;
  signal A,B,Q:std_logic_vector(7 downto 0);
  signal P:std_logic_vector(2 downto 0);
  signal C,Z:std_logic;
begin
  Z<=(P(2)AND P(1))AND P(0);
  MULT_OUT<=A&Q;

state_register:process (CLK,RESET)
begin
    if(RESET='1')then
      state<=IDLE;
    elsif(CLK'event and CLK='1')then
      state<=next_state;
    end if;
end process;

next_state_func:process(G,Z,state)
begin
    case state is
     when IDLE=>
      if G='1' then
        next_state<=MUL0;
      else
        next_state<=IDLE;
      end if;
    when MUL0=>
      next_state<=MUL1;
    when MUL1=>
      if Z='1' then
        next_state<=IDLE;
      else
        next_state<=MUL0;
      end if;
    end case;
end process;

datapath_func:process(CLK)
variable CA:std_logic_vector(8 downto 0);
begin
    if(CLK'event and CLK='1')then
      if LOADB='1' then
        B<=MULT_BIN;
      end if;
      if LOADQ='1' then
        Q<=MULT_QIN;
      end if;
      case state is
       when IDLE=>
        if G='1' then
          C<='0';
          A<="00000000";
          P<="000";
        end if;
       when MUL0=>
        if Q(0)='1' then
          CA:=('0'&A)+('0'&B);
        else
          CA:=C&A;
        end if;
         C<=CA(8);
         A<=CA(7 downto 0);
       when MUL1=>
         C<='0';
         A<=C&A(7 downto 1);
         Q<=A(0)&Q(7 downto 1);
         P<=P+"001";
       end case;
    end if;
  end process;
end behavior_8;